Robert A Sheldon

US Patent:

51464608, Sep 8, 1992

Filed:

Feb 16, 1990

Appl. No.:

7/481145

Inventors:

Dennis F. Ackerman - Beacon NY
David R. Bender - Poughkeepsie NY
Salina S. Chu - Poughkeepsie NY
George R. Deibert - Staatsburg NY
Gary G. Hallock - Pleasant Valley NY
David E. Lackey - Poughkeepsie NY
Robert G. Sheldon - Pleasant Valley NY
Thomas A. Stranko - Poughkeepsie NY

Assignee:

International Business Machines - Armonk NY

International Classification:

G06G 748

US Classification:

371 23

Abstract:

Software simulators of logic design circuits run slowly but are capable of providing very finely detailed error trace analyses. On the other hand, hardware accelerators operating to perform similar functions are very fast in their execution but are not capable of practically isolating error states or other critical conditions. Accordingly, the present invention provides an interactive system combining software simulators and hardware accelerators so that when desired test results do not favorably compare with simulated results, a mechanism is provided for storing the current hardware accelerator state and restoring the accelerator to a previous checkpoint state which has been saved as a result of a prior periodic interruption. The hardware accelerator is then operated for a time sufficient to bring it up to a state that occurs just before the detected miscomparison. At this point, state information from the hardware accelerator is supplied to a software simulator for detailed error analysis and fault tracing.