Robert B Staszewski

US Patent:

6414555, Jul 2, 2002

Filed:

Feb 22, 2001

Appl. No.:

09/790376

Inventors:

Robert B. Staszewski - Garland TX
Dirk Leipold - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03L 718

US Classification:

331 18, 331 16, 327105, 327156

Abstract:

A frequency synthesizer ( ) includes a DDFS ( ) and a PLL loop ( ). The oscillator frequency signal ( ) is used to create the DDFS clock signal ( ), f that acts as a system clock for the DDFS ( ). With the phase/frequency state of the DDFS being adjusted based on a comparison of the DDFS system clock signal ( ) with a frequency reference signal ( ), f. The DDFS system clock signal ( ) is further divided by a divider ( ) to establish an update clock signal ( ), f. The output of the DDFS and the update clock signal ( ) are compared by a phase/frequency detector ( ). The output signal of the PFD ( ) is preferably filtered by a loop filter ( ) before using it as a tuning signal ( ) for the DCO ( ). The principle of bootstraping ensures that the synthesizer ( ) is synchronous and every clock is derived from the same source.

US Patent:

6429693, Aug 6, 2002

Filed:

Jun 30, 2000

Appl. No.:

09/608317

Inventors:

Robert B. Staszewski - Garland TX
Dirk Leipold - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03D 324

US Classification:

327 12, 327 3, 327158, 327107

Abstract:

A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.

US Patent:

6442197, Aug 27, 2002

Filed:

Feb 26, 1999

Appl. No.:

09/258594

Inventors:

Robert B. Staszewski - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03H 730

US Classification:

375229, 375232, 375233, 375231

Abstract:

A method and system for performing a timing recovery acquisition of a sinusoidal preamble with reduced loop latency by effectively bypassing the FIR filter out of the timing loop. The method is implemented by estimating the FIR filters ( ) phase shift through knowing its coefficients a priori while also determining the phase error at the FIR filters input. Because of the non-symmetric settings of the coefficients the phase shift through the FIR may not be zero. It reduces the latency of a non-data tracking timing loop by eliminating latency due to the FIR filter ( ) itself. The coefficients can be either programmed in memory ( ) or adapted as part of an LMS application. The estimate avoids the use of multiply operations, using add operations and a single divider. The estimated partial phase errors are then summed in a âFIR bypass-modeâ phase detector ( ) yielding total phase shift.

US Patent:

6523052, Feb 18, 2003

Filed:

Oct 29, 1999

Appl. No.:

09/430385

Inventors:

Robert B. Staszewski - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1710

US Classification:

708322, 360 65

Abstract:

A method and circuit ( ) for achieving a fast EPR4 equalization start-up for an FIR filter ( ) in a magnetic recording read channel is presented in which a three-level adaptation in an LMS coefficient equalizer ( ) at an FIR output ( ) is performed to provide a rough estimate of coefficients to said FIR filter ( ). A 1+D operation ( ) on the FIR output ( ) is performed to generate an indirect mode EPR4 equalized signal ( ), which may be applied to an input of a detector ( ) of the read channel. After a predetermined time, the EPR4 equalized signal ( ) is used to perform a five-level adaptation in the LMS coefficient equalizer ( ) to provide a fine estimate of coefficients to said FIR filter ( ). The method utilizes the robustness of a three-level PR4-target LMS adaptation of the EPR4 read channel in order to establish an initial setting of the coefficients of a newly-built system, which does not have very well known channel characteristics. With the initial FIR coefficients being in the neighborhood of the final coefficients, a more refined adaptation method can be used.

US Patent:

6587529, Jul 1, 2003

Filed:

Feb 25, 1999

Appl. No.:

09/258827

Inventors:

Robert B. Staszewski - Garland TX
Fulvio Spagna - San Jose CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04L 2500

US Classification:

375371, 360 51

Abstract:

A system and method for enabling an efficient Zero Phase Restart (ZPR) of a device. The structure is based on deploying normalized timing gradient (NTG) blocks ( and ) in pairs, each circuit employing an orthogonal phase error transfer function characteristic (having one TG circuit sample orthogonally in relation to the other), for example, PR4 and EPR4 modes ideal sampling instances of a preamble. An NTG block ( or ) is selected based on having a native timing sampling instance with a phase error that is closest to zero. Since there is an equal chance that either of the circuits in a circuit pair will be selected, if the circuit implementing the current non-native architecture is selected, a separate signal is generated. This signal adds the equivalent of 180Â to the error value that is provided to the timing recovery circuit. For example, by iterating the process after the special case of a zero phase restart (ZPR) operation, the native sampling instance is âforcedâ to be selected thereafter.

US Patent:

6593773, Jul 15, 2003

Filed:

Sep 28, 2001

Appl. No.:

09/967275

Inventors:

Robert B. Staszewski - Garland TX
Dirk Leipold - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03D 324

US Classification:

326 46, 327 12, 327 3, 327158, 327107

Abstract:

To conserve power in a circuit where a high-speed signal HSIG controls combinational logic ( ), while a low-speed signal LCLK drives a logic/memory circuit ( ) that samples the output of the combinational logic, predictive logic state machine ( ) generates a clock, P_LCLK, which has an active level preceding the active edge of LCLK by a period sufficient to allow the combinational logic to reach the desired state prior to the active edge of LCLK and, preferably, allows for possible jitter in LCLK. Responsive to P_LCLK, the signal suspend circuitry ( ) either passes HSIG or gates off HSIG. Further reductions in power can be accomplished by predicting which portions of the logic/memory circuit ( ) will be used, and clocking those portions.

US Patent:

6606004, Aug 12, 2003

Filed:

Apr 19, 2001

Appl. No.:

09/838451

Inventors:

Robert B Staszewski - Garland TX
Kenneth Maggio - Dallas TX
Dirk Leipold - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03L 700

US Classification:

331 17, 331 78

Abstract:

A technique of time dithering a fully digitally-controlled oscillator (DCO) tuning input employs a shift register and a multiplexer responsive to a sigma-delta modulated delay control to minimize spurious tones generated by a DCO. The shift register is clocked via a divided-down high-frequency reference provided by the DCO output signal. The multiplexer is clocked via a frequency reference that is reclocked and synchronized to the DCO output signal. The multiplexer output is thus time dithered in response to a delay control to minimize perturbations caused by switching.

US Patent:

6618740, Sep 9, 2003

Filed:

Oct 1, 1999

Appl. No.:

09/410510

Inventors:

Robert B. Staszewski - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1710

US Classification:

708322

Abstract:

A circuit ( ) and method, which can be used in a mass data storage device, controls adaptation asymmetry of coefficients of an FIR filter ( ) using an accumulator ( ) for accumulating correlation results between unequalized FIR filter input data samples and FIR filter output equalized error samples. A circuit ( ) generates coefficient increment and decrement requests from the accumulated correlation results. A circuit ( ) updates the coefficients within a symmetric coefficient pair on the basis of the increment and decrement requests only if a predetermined nonzero coefficient magnitude difference between the coefficient pair would not be exceeded by the update. In one embodiment of the invention, circuit ( ) and method are provided for generating coefficients for an FIR filter in a sign-sign LMS algorithm using an accumulator for accumulating in a sub-least significant bit register ( ) successive sign values of an error between input data samples to the FIR filter and output error samples from the FIR filter and an increment/decrement circuit ( ) to request an increment/decrement of a coefficient value of the FIR filter on the basis of carry-out and borrow-in operations of the sub-least significant bit register ( ).

Address:

413 W Muirfield Rd, Garland, TX 75044

VIN:

5N1BV28U27N105502

Make:

NISSAN

Model:

QUEST

Year:

2007