Robert M Supnik

US Patent:

7401355, Jul 15, 2008

Filed:

Apr 30, 2004

Appl. No.:

10/835794

Inventors:

Robert M. Supnik - Carlisle MA, US
David S. Caplan - Acton MA, US
Paul G. Phillips - Westboro MA, US
Michael Banatt - Cambridge MA, US

Assignee:

Sun Microsystems - Santa Clara CA

International Classification:

H04L 29/00

US Classification:

726 11

Abstract:

Methods and systems for load balancing a plurality of entities, such as firewalls, in a network environment are disclosed. In particular, the load balancing of firewalls on a bidirectional traffic path is performed using a single device that controls both incoming and outgoing traffic through the firewalls. The single device may include virtual routers for controlling the bidirectional traffic through the firewalls. A first virtual router may control incoming traffic to the firewalls and the other virtual router may control outgoing traffic to the firewalls. The virtual routers are logical partitions of the device layered on the physical resources of the device. The virtual routers share all or portions of the physical resources of the single device.

US Patent:

50705024, Dec 3, 1991

Filed:

Jun 23, 1989

Appl. No.:

7/370469

Inventors:

Robert M. Supnik - Carlisle MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1120

US Classification:

371 111

Abstract:

It is desirable to bypass the defects within a cache memory so that a high percentage of the cache is usable; otherwise the entire chip containing the cache memory must be scrapped. Since VLSI chips with a small number of defects form a large proportion of the scrapped yield, rendering chips with a small number of defects usable greatly increases the production yield and reduces the cost of each chip. Therefore, a cache memory is provided wherein each memory location includes a bit which is set in response to a detected hardware defect. Preferably, each memory location in the cache is tested by error detecting software, which sets the defect bit in any memory location containing a defect. The defect bit is tested every time data is retrieved from each memory location, and a set defect bit prohibits further use of a defective memory location.

US Patent:

50438670, Aug 27, 1991

Filed:

Mar 18, 1988

Appl. No.:

7/170393

Inventors:

Dileep P. Bhandarkar - Shrewsbury MA
Robert Supnik - Carlisle MA
Steven Hobbs - Westford MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A data process system capable of executing vector instructions and scalar instructions detects the occurrence of arithmetic exception conditions and allows subsequent scalar instruction processing until execution of the next vector instruction is required.

US Patent:

48519910, Jul 25, 1989

Filed:

Feb 24, 1987

Appl. No.:

7/017518

Inventors:

Paul I. Rubinfeld - Wayland MA
G. Michael Uhler - Marlboro MA
Robert M. Supnik - Carlisle MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A processor for use in a digital data processing system including a main memory and a write buffer for buffering write data and associated addresses from the processor for storage in the storage locations identified by the associated addresses in the main memory. In response to selection occurances, such as a context switch, which cannot be detected outside of the processor, the processor asserts a signal which enables the write buffer to transfer all of its contents to the main memory. The write buffer, in turn, disables the processor while it is transferring data to the main memory.

US Patent:

52768929, Jan 4, 1994

Filed:

Sep 16, 1992

Appl. No.:

7/945856

Inventors:

Andrew S. Olesin - Princeton MA
Robert M. Supnik - Carlisle MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 946

US Classification:

395775

Abstract:

A processor for use in a digital data processing system includes a data path which is controlled by microinstructions from the processor's control circuits. The data path includes a plurality of registers and an arithmetic and logic unit. The source data processed by the arithmetic and logic unit is obtained from the registers and elsewhere in the system as identified by selected fields of the microinstruction, and the processed data is stored in destinations also identified by the source selection fields or other locations. The destination selection field of the microinstruction selects a source identification or another destination as the selected destination.

US Patent:

49492500, Aug 14, 1990

Filed:

Mar 18, 1988

Appl. No.:

7/170395

Inventors:

Dileep P. Bhandarkar - Shrewsbury MA
Robert Supnik - Carlisle MA
Tryggve Fossum - Northboro MA
Dwight Manley - Holliston MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 15347

US Classification:

364200

Abstract:

A data processing system containing a vector processor and a scalar processor executes scalar and vector instructions which both comprise an operation portion and an operand pointer portion. In the vector instructions, however, the operand pointer portion contains an operand specifier which identifies a vector control word. Each vector control word contains, for the corresponding vector instruction, flags and vector operand pointers. The vector operand pointers specify vector registers in the vector processor. The flags contain additional information for the execution of the vector instructions.

US Patent:

20160266813, Sep 15, 2016

Filed:

Mar 9, 2015

Appl. No.:

14/641587

Inventors:

Robert Supnik - Carlisle MA, US

Assignee:

UNISYS CORPORATION - Blue Bell PA

International Classification:

G06F 3/06

Abstract:

A method for reading data is provided. The method comprises receiving, via a storage subsystem controller, over a fabric, a read command from a host device. The method further comprises locating, via the storage subsystem controller, over the fabric, based at least in part on the read command, read data in a flash main memory of a node device. The method also comprises facilitating, via the storage subsystem controller, an establishment of a remote direct memory access connection between the flash main memory of the node device and the host device over the fabric such that the read data is communicable from the flash main memory of the node device to the host device over the fabric.

US Patent:

20160267050, Sep 15, 2016

Filed:

Mar 9, 2015

Appl. No.:

14/641592

Inventors:

Robert Supnik - Carlisle MA, US

Assignee:

UNISYS CORPORATION - Blue Bell PA

International Classification:

G06F 15/167
H04L 29/08
G06F 3/06

Abstract:

A method for writing data is provided. The method comprises receiving, via a storage subsystem controller, over a fabric, a write command from a host device. The method further comprises identifying, via the storage subsystem controller, over the fabric, based at least in part on the write command, a flash main memory of a node device on which to store write data associated with the write command. The method also comprises facilitating, via the storage subsystem controller, an establishment of a remote direct memory access connection between the host device and the flash main memory of the node device over the fabric such that the write data is communicable from the host device to the flash main memory of the node device over the fabric.