Robert D Todd

US Patent:

20050145922, Jul 7, 2005

Filed:

Dec 30, 2003

Appl. No.:

10/748497

Inventors:

Joseph Farley - Villeneuve Loubet, FR
Jozef Mitros - Richardson TX, US
Alec Morton - Plano TX, US
Robert Todd - Plano TX, US

International Classification:

H01L029/788

US Classification:

257315000

Abstract:

An EEPROM memory cell uses PMOS type floating gate transistor formed in a n-well, where the floating gate is routed over a p− diffused region formed in the n-well to form a control capacitor. The PMOS floating gate transistor uses a p-type diffused region below the p+ active region forming the drain to provide a higher breakdown voltage. Cell programming can be performed through hot-electron injection, with the electric field across the control capacitor to aid injection into the floating gate. FN erasure is achieved by taking the potential of the n-well to the programming voltage while holding the potential of the control capacitor at a low voltage.

US Patent:

20060279009, Dec 14, 2006

Filed:

Mar 28, 2005

Appl. No.:

11/090994

Inventors:

Greg Hall - Arlington TX, US
Minnie Hall - Arlington TX, US
Robert Todd - Viera FL, US
Clois Todd - Viera FL, US

International Classification:

B01F 3/04

US Classification:

261116000, 261DIG088, 261026000

Abstract:

A device injecting a deodorant through an atomizing nozzle into the “output” duct of a home Heat and Air Conditioning System. The device may be used in other areas such as small businesses and may be used to inject disinfectant.

US Patent:

20200161471, May 21, 2020

Filed:

Jan 23, 2020

Appl. No.:

16/750020

Inventors:

- Dallas TX, US
Robert James Todd - Plano TX, US
Henry Litzmann Edwards - Garland TX, US

International Classification:

H01L 29/78
H01L 29/66
H01L 21/285
H01L 21/225
H01L 21/324
H01L 21/265
H01L 21/762
H01L 21/74
H01L 29/10
H01L 29/40
H01L 29/06

Abstract:

A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.

US Patent:

20190172946, Jun 6, 2019

Filed:

Dec 4, 2017

Appl. No.:

15/830856

Inventors:

- Dallas TX, US
Robert James Todd - Plano TX, US
Henry Litzmann Edwards - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/78
H01L 29/10
H01L 29/06
H01L 29/40
H01L 29/66
H01L 21/762
H01L 21/265
H01L 21/324
H01L 21/225
H01L 21/285
H01L 21/74

Abstract:

A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.