Robert P Vaudo

US Patent:

6440823, Aug 27, 2002

Filed:

Oct 26, 1998

Appl. No.:

09/179049

Inventors:

Robert P. Vaudo - New Milford CT
Vivek M. Phanse - Cambridge MA
Michael A. Tischler - Phoenix AZ

Assignee:

Advanced Technology Materials, Inc. - Danbury CT

International Classification:

H01L 2120

US Classification:

438478, 483 22

Abstract:

A low defect density (Ga,Al,In)N material. The (Ga, Al, In)N material may be of large area, crack-free character, having a defect density as low as 3Ã10 defects/cm or lower. Such (Ga,Al,In)N material is useful as a substrate for epitaxial growth of Group III-V nitride device structures thereon.

US Patent:

6447604, Sep 10, 2002

Filed:

Jun 28, 2000

Appl. No.:

09/605195

Inventors:

Jeffrey S. Flynn - Litchfield CT
George R. Brandes - Southbury CT
Robert P. Vaudo - New Milford CT
David M. Keogh - San Diego CA
Xueping Xu - Stamford CT
Barbara E. Landini - New Milford CT

Assignee:

Advanced Technology Materials, Inc. - Danbury CT

International Classification:

C30B 2514

US Classification:

117 89, 117 93, 117 94, 117 95, 117952

Abstract:

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e. g. , of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 10 , nitrogen source material partial pressure in a range of from about 1 to about 10 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0. 1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

US Patent:

6488767, Dec 3, 2002

Filed:

Jun 8, 2001

Appl. No.:

09/877437

Inventors:

Xueping Xu - Stamford CT
Robert P. Vaudo - New Milford CT

Assignee:

Advanced Technology Materials, Inc. - Danbury CT

International Classification:

C30B 2502

US Classification:

117 2, 117 1, 117 90, 117 92, 117 97, 117106, 117109

Abstract:

A high quality wafer comprising Al Ga In N, wherein 0y1 and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10Ã10 m area at its Ga-side. Such wafer is chemically mechanically polished (CMP) at its Ga-side, using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. The process of fabricating such high quality Al Ga In N wafer may include steps of lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. The CMP process is usefully employed to highlight crystal defects on the Ga-side of the Al Ga In N wafer.

US Patent:

6533874, Mar 18, 2003

Filed:

Sep 7, 2000

Appl. No.:

09/656595

Inventors:

Robert P. Vaudo - New Milford CT
Joan M. Redwing - Phoenix AZ
Michael A. Tischler - Phoenix AZ
Duncan W. Brown - La Jolla CA
Jeffrey S. Flynn - Wolcott CT

Assignee:

Advanced Technology Materials, Inc. - Danbury CT

International Classification:

H01L 2906

US Classification:

148 335, 257 76, 257103, 257615

Abstract:

A method of forming a (gallium, aluminum, indium) nitride base layer on a substrate for subsequent fabrication, e. g. , by MOCVD or MBE, of a microelectronic device structure thereon. Vapor-phase (Ga, Al, In) chloride is reacted with a vapor-phase nitrogenous compound in the presence of the substrate, to form (Ga, Al, In) nitride. The (Ga, Al, In) nitride base layer is grown on the substrate by HVPE, to yield a microelectronic device base comprising a substrate with the (Ga, Al, In) nitride base layer thereon. The product of such HVPE process comprises a device quality, single crystal crack-free base layer of (Ga, Al, In) N on the substrate, in which the thickness of the base layer may, for example, be on the order of 2 microns and greater and the defect density of the base layer may, for example, be on the order of 1E8 cm or lower. Microelectronic devices thereby may be formed on the base layer, over a substrate of a foreign (poor lattice match) material, such as sapphire. Devices which may be fabricated utilizing the HVPE base layer of the invention include light emitting diodes, detectors, transistors, and semiconductor lasers.

US Patent:

6596079, Jul 22, 2003

Filed:

Mar 13, 2000

Appl. No.:

09/524062

Inventors:

Robert P. Vaudo - New Milford CT
Jeffrey S. Flynn - Litchfield CT
George R. Brandes - Southbury CT
Joan M. Redwing - State College PA
Michael A. Tischler - Phoenix AZ

Assignee:

Advanced Technology Materials, Inc. - Danbury CT

International Classification:

C30B 2306

US Classification:

117 97, 117 87, 117 88, 117 89, 117 95, 117101, 117952

Abstract:

A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e. g. , having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 10 defects cm. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour.

US Patent:

6765240, Jul 20, 2004

Filed:

Aug 21, 2001

Appl. No.:

09/933943

Inventors:

Michael A. Tischler - Phoenix AZ
Thomas F. Kuech - Madison WI
Robert P. Vaudo - New Milford CT

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 310328

US Classification:

257183, 257200, 257615

Abstract:

A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e. g. , with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.

US Patent:

6943095, Sep 13, 2005

Filed:

Mar 21, 2002

Appl. No.:

10/103226

Inventors:

Robert P. Vaudo - New Milford CT, US
Vivek M. Phanse - Cambridge MA, US
Michael A. Tischler - Phoenix AZ, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L021/20

US Classification:

438479, 438483

Abstract:

A low defect density (Ga,Al,In)N material. The (Ga, Al, In)N material may be of large area, crack-free character, having a defect density as low as 3×10defects/cmor lower. Such (Ga,Al,In)N material is useful as a substrate for epitaxial growth of Group III-V nitride device structures thereon.

US Patent:

6951695, Oct 4, 2005

Filed:

Oct 17, 2002

Appl. No.:

10/272761

Inventors:

Xueping Xu - Stamford CT, US
Robert P. Vaudo - New Milford CT, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

B32B009/04
B24B001/00
H01L021/302

US Classification:

428698, 428689, 428697, 438691, 438692, 438693, 451 36, 451 37, 451 57

Abstract:

AlGaInN, wherein 0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10×10 μmarea. The AlGaInN may be in the form of a wafer, which is chemically mechanically polished (CMP) using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. High quality AlGaInN wafers can be fabricated by steps including lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. CMP processing may be usefully employed to highlight crystal defects of an AlGaInN wafer.