Robert H Wisniewski

US Patent:

8051276, Nov 1, 2011

Filed:

Jul 7, 2006

Appl. No.:

11/482270

Inventors:

Orran Y. Krieger - Newton MA, US
Bryan S. Rosenburg - Cortlandt Manor NY, US
Robert B. Tremaine - Stormville NY, US
Robert W. Wisniewski - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/38

US Classification:

712220

Abstract:

A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling threads. In one aspect, the observed temperature values are recorded on registers. An operating system or the like reads the registers and schedules threads based on the temperature values.

US Patent:

8495649, Jul 23, 2013

Filed:

Jul 19, 2006

Appl. No.:

11/488970

Inventors:

Orran Y. Krieger - Newton MA, US
Bryan S. Rosenburg - Cortlandt Manor NY, US
Balaram Sinharoy - Poughkeepsie NY, US
Robert B. Tremaine - Stormville NY, US
Robert W. Wisniewski - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46

US Classification:

718105

Abstract:

A method and system for scheduling threads on simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system determines thread scheduling based on the information.

US Patent:

20080022283, Jan 24, 2008

Filed:

Jul 19, 2006

Appl. No.:

11/488977

Inventors:

Orran Y. Krieger - Newton MA, US
Bryan S. Rosenburg - Cortlandt Manor NY, US
Robert B. Tremaine - Stormville NY, US
Robert W. Wisniewski - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46

US Classification:

718104

Abstract:

A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.

US Patent:

20080229321, Sep 18, 2008

Filed:

May 30, 2008

Appl. No.:

12/130612

Inventors:

Orran Y. Krieger - Newton MA, US
Bryan S. Rosenburg - Cortlandt Manor NY, US
Robert B. Tremaine - Stormville NY, US
Robert W. Wisniewski - Ossining NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 9/50

US Classification:

718104

Abstract:

A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.

US Patent:

20100250853, Sep 30, 2010

Filed:

Jul 7, 2006

Appl. No.:

11/482222

Inventors:

Orran Y. Krieger - Newton MA, US
Balaram Sinharoy - Poughkeepsie NY, US
Robert B. Tremaine - Stormville NY, US
Robert W. Wisniewski - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/10
G06F 12/08
G06F 13/24

US Classification:

711122, 711206, 710269, 711E12017, 711E12059

Abstract:

A method and system for prefetching in computer system are provided. The method in one aspect includes using a prefetch engine to perform prefetch instructions and to translate unmapped data. Misses to address translations during the prefetch are handled and resolved. The method also includes storing the resolved translations in a respective cache translation table. A system for prefetching in one aspect includes a prefetch engine operable to receive instructions to prefetch data from the main memory. The prefetch engine is also operable to search cache address translation for prefetch data and perform address mapping translation, if the prefetch data is unmapped. The prefetch engine is further operable to prefetch the data and store the address mapping in one or more cache memory, if the data is unmapped.

US Patent:

20160179587, Jun 23, 2016

Filed:

Dec 17, 2014

Appl. No.:

14/573133

Inventors:

Clement T. Cole - Chelmford MA, US
James Dinan - Hudson MA, US
Gabriele Jost - Santa Clara CA, US
Stanley C. Smith - Hillsboro OR, US
Robert W. Wisniewski - Ossining NY, US
Keith D. Underwood - Albuquerque NM, US

International Classification:

G06F 9/54
G06F 12/06

Abstract:

A method comprising receiving control information at a first processing element from a second processing element, synchronizing objects within a shared global memory space of the first processing element with a shared global memory space of a second processing element in response to receiving the control information and generating a completion event indicating the first processing element has been synchronized with the second processing element.