Robert G Wisniewski

US Patent:

6460059, Oct 1, 2002

Filed:

Aug 4, 1998

Appl. No.:

09/129490

Inventors:

Robert William Wisniewski - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1700

US Classification:

707503, 707504, 707506

Abstract:

A method and apparatus for displaying a spreadsheet on a display device in a computer system to facilitate easy recognition of errors. More specifically, with this invention one cell is selected, and there is a visual indication of such selection. Further, there is also a visual indication of those cells having data that either affects or depends upon the data in the selected cell. There is also a different visual indication for each level of dependency relative to the selected cell. For example, selected cell A may be immediately dependent upon cells B and C, where cell B may in turn be dependent upon cells D, E and F. Cells B and C are at the first level of dependency while cells D, E and F are at the second level of dependency. Thus, cells B and C may have a different marking or shading than cells D, E and F. The number of dependency levels to be displayed can be chosen by the user.

US Patent:

6587865, Jul 1, 2003

Filed:

Sep 21, 1998

Appl. No.:

09/157479

Inventors:

Tracy Jay Kimbrel - Yorktown Heights NY
Marc Alan Auslander - Millwood NY
David Joel Edelsohn - White Plains NY
Hubertus Franke - Cortlandt Manor NY
Orran Yaakov Krieger - Brookline MA
Bryan Savoye Rosenburg - Cortlandt Manor NY
Robert William Wisniewski - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

709104, 709100, 709103, 711141, 711145

Abstract:

In a computer system, a method and apparatus for scheduling activities access to a resource with minimal involvement of the kernel of the operating system. More specifically, a ânext bidâ is maintained, and this parameter identifies the highest bid for the resource by any activity not currently accessing the resource. The accessing activity then compares its bid, which can be time varying, with the ânext bidâ to determine whether it should release the resource to another activity. The ânext bidâ can be accessed without any system calls to the operating system. This allows the activity to determine whether to relinquish control to the system without the necessity of communication between the two. Likewise, the operating system can access the bid of the accessing activity without explicit communication. This allows the system to determine whether to preempt the accessing activity without the necessity of communication between the two.

US Patent:

6601146, Jul 29, 2003

Filed:

Jun 16, 1998

Appl. No.:

09/098061

Inventors:

Marc Alan Auslander - Millwood NY
David Joel Edelsohn - White Plains NY
Hubertus Franke - Cortlandt Manor NY
Orran Yaakov Krieger - Brookline MA
Bryan Savoye Rosenburg - Cortlandt Manor NY
Robert William Wisniewski - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711147, 711202

Abstract:

A method and apparatus for performing efficient interprocess communication (IPC) in a computer system. With this invention, a memory region called the IPC transfer region is shared among all processes of the system to enable more efficient IPC. The unique physical address of the region is mapped into a virtual address from each of the address spaces of the processes of the system. When one of the processes needs to transfer data to another of the processes, the first process stores arguments describing the data in the region using the virtual address in its address space that maps into the unique physical address. When the other or second process needs to receive the data, the second process reads the data from the second region using the virtual address in its memory space that maps into the unique physical address. With this invention, in most cases, control of the IPC transfer region occurs automatically without any kernel intervention.

US Patent:

7315950, Jan 1, 2008

Filed:

Dec 20, 1999

Appl. No.:

09/468377

Inventors:

Yurij Andrij Baransky - Montrose NY, US
Hubertus Franke - Cortlandt Manor NY, US
Pratap Chandra Pattnaik - Ossining NY, US
David R. Safford - Brewster NY, US
Robert William Wisniewski - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 21/00

US Classification:

713193

Abstract:

A method for allowing a content provider to restrict access to data without having to trust a service provider. With this invention a content provider is able to restrict access to data to a specific client using a specific machine. A content provider generates a first key which is used to encrypt a second key where the second key will only be encrypted if the user has a one-time password. The encrypted second key is then stored on the client machine. When the user desires to access the data of the content provider, the second key is decrypted and used to access the data.

US Patent:

7376808, May 20, 2008

Filed:

Jan 31, 2006

Appl. No.:

11/343565

Inventors:

Gheorghe Calin Cascaval - Carmel NY, US
Evelyn Duesterwald - New York NY, US
Peter F. Sweeney - Spring Valley NY, US
Robert W. Wisniewski - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/34
G06F 12/00

US Classification:

711207, 711202, 711203, 711206, 703 13, 703 14, 703 21, 703 22

Abstract:

A method for modeling the performance of memory address translation mechanism (MATM), comprises: a) receiving an execution profile that contains a memory address reference stream of an application, a set of page size mappings, and events about the application's data allocations and de-allocations; b) translating each memory reference in the input memory reference stream into a reference to the corresponding data object, by consulting the memory allocation and de-allocation events, to provide a data object reference stream; c) translating each data object reference into a corresponding page reference by consulting the page size mapping and by modeling the data allocation and de-allocation events in accordance with the mapping to provide a page reference stream and a number of pages of each page size that are needed by the respective mapping; d) using the page reference stream to provide a stream of reuse distance values; e) determining, for each reference in the reuse distance value stream, whether the reference results in a hit or a miss reference to the MATM to provide the number of hits and the number of misses for each MATM; f) providing the hit and miss values to a cost model to estimate the number of miss cycles; g) ranking the mappings by their miss cycle values such that the mapping with the lowest number of miss cycles has the highest rank.

US Patent:

7467280, Dec 16, 2008

Filed:

Jul 5, 2006

Appl. No.:

11/481020

Inventors:

Xiaowei Shen - Hopewell Junction NY, US
Balaram Sinharoy - Poughkeepsie NY, US
Robert B. Tremaine - Stormville NY, US
Robert W. Wisniewski - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711170, 711122, 711129, 711144, 711145, 713300, 713320, 702130

Abstract:

A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

US Patent:

7533377, May 12, 2009

Filed:

Sep 29, 2003

Appl. No.:

10/673587

Inventors:

Jonathan Appavoo - Yorktown Heights NY, US
Marc Alan Auslander - Millwood NY, US
Kevin Kin-Fai Hui - Kitchener, CA
Orran Yaakov Krieger - Newton MA, US
Dilma Menezes Da Silva - White Plains NY, US
Robert William Wisniewski - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/44
G06F 15/177

US Classification:

717168, 713 2

Abstract:

Systems, especially operating systems, are becoming more complex to the point where maintaining them by humans is becoming nearly impossible. Many corporations have recognized this trend and have begun investing in autonomic technology. Autonomic technology allows a piece of software to monitor, diagnose, and repair itself. This can be used for improved performance, reliability, maintainability, security, etc. Disclosed herein is a mechanism to allow operating systems to hot swap a piece of operating system code, while continuing to offer to the user the service which that code is providing. This can be used, for examples, to increase the performance of an application or to fix a detected security hole live without bringing the machine down. Some autonomic ability will be mandatory in next generation operating system for without it they will collapse under their own complexity. The invention offers a key component of being able to achieve autonomic computing.

US Patent:

7574562, Aug 11, 2009

Filed:

Jul 21, 2006

Appl. No.:

11/491413

Inventors:

Xiaowei Shen - Hopewell Junction NY, US
Balaram Sinharoy - Poughkeepsie NY, US
Robert W. Wisniewski - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/02

US Classification:

711118, 711119

Abstract:

A system and method for latency-aware thread scheduling in non-uniform cache architecture are provided. Instructions may be provided to the hardware specifying in which banks to store data. Information as to which banks store which data may also be provided, for example, by the hardware. This information may be used to schedule threads on one or more cores. A selected bank in cache memory may be reserved strictly for selected data.