Robert C Yung

US Patent:

6385713, May 7, 2002

Filed:

Jan 4, 2001

Appl. No.:

09/756023

Inventors:

Robert Yung - Fremont CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 9302

US Classification:

712 22, 708500, 708502, 712222

Abstract:

An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executing them are disclosed to optimize the execution of graphics instruction with minimal additional hardware for a general purpose CPU.

US Patent:

6396504, May 28, 2002

Filed:

Jul 1, 1996

Appl. No.:

08/674278

Inventors:

Robert Yung - Fremont CA
Carlan Joseph Beheler - Foster City CA
Jaijiv Prabhakaran - Sunnyvale CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06T 1100

US Classification:

345589

Abstract:

An image processor converts single-band pixel components, each of which represents a single band of a multiple-band pixel, to multiple-band pixels. A embodiment, a single read operation reads four single-band pixel components from each of three buffers which correspond to red, green, and blue bands, respectively, of a multiple-band graphical image. A single merge operation merges eight single-band pixel components representing alpha and green bands of four multiple-band pixels, and a single merge operation merges eight single-band pixel components representing blue and red bands of four multiple-band pixels. Two merge operations merge the respective merged data words to form four multiple-band pixels, each of which includes alpha, blue, green, and red components. The four multiple-band pixels are written to a destination buffer in four write operations.

US Patent:

20020091910, Jul 11, 2002

Filed:

Mar 7, 2002

Appl. No.:

10/094454

Inventors:

Robert Yung - Fremont CA, US

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F015/00

US Classification:

712/022000

Abstract:

An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executing them are disclosed to optimize the execution of graphics instruction with minimal additional hardware for a general purpose CPU.

US Patent:

20020124162, Sep 5, 2002

Filed:

Aug 13, 2001

Appl. No.:

09/927346

Inventors:

Robert Yung - Fremont CA, US
Kit Tam - San Bruno CA, US
Alfred Yeung - San Francisco CA, US
William Joy - Aspen CO, US

Assignee:

Sun Microsystems, Inc.

International Classification:

G06F009/00
G06F015/00

US Classification:

712/238000

Abstract:

N instruction class (IClass) fields, m branch prediction (BRPD) and k next fetch address fields are added to each instruction set of n instructions of a cache line of an instruction cache, where m and k are less than or equal to n. The BRPD and NFAPD fields of a cache line are initialized in accordance to a pre-established initialization policy of a branch and next fetch address prediction algorithm while the cache line is first brought into the instruction cache. The sets of IClasses, BRPDS, and NFAPDs of a cache line are accessed concurrently with the corresponding sets of instructions of the cache line. One BRPD and one NFAPD is selected from the set of BRPDs and NFAPDs corresponding to the selected set of instructions. The selected BRPD and NFAPD are updated in accordance to a pre-established update policy of the branch and next fetch address prediction algorithm when the actual branch direction and next fetch address are resolved. Additionally, in one embodiment, m and k are equal to 1, and the selected NFAPD is stored immediately into the NFA register of the instruction prefetch and dispatch unit, allowing the selected NFAPD to be used as the fetch address for the next instruction cache access to achieve zero fetch latency for both control transfer and sequential next fetch.

US Patent:

59331577, Aug 3, 1999

Filed:

Apr 19, 1996

Appl. No.:

8/635271

Inventors:

Timothy J. Van Hook - Menlo Park CA
Leslie Dean Kohn - Fremont CA
Robert Yung - Fremont CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G09G 500

US Classification:

345513

Abstract:

The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor and a graphics data alignment address offset. Additionally, the CPU is provided with a graphics execution unit (GRU) for executing a number of graphics operations in accordance to the graphics data scaling factor and alignment address offset, the graphics data having a number of graphics data formats. In one embodiment, the GRU is also used to execute a number of graphics data addition, subtraction, rounding, expansion, merge, alignment, multiplication, logical, compare, and pixel distance operations. The graphics data operations are categorized into a first and a second category, and the GRU concurrently executes one graphics operations from each category. Furthermore, under this embodiment, the IEU is also used to execute a number of graphics data edge handling and 3-D array addressing operations, while the load and store unit (LSU) of the CPU is also used to execute a number of graphics data load and store operations, including conditional store operations.

US Patent:

57272190, Mar 10, 1998

Filed:

May 9, 1997

Appl. No.:

8/854113

Inventors:

Thomas L. Lyon - Palo Alto CA
Sun-Den Chen - San Jose CA
William Joy - Aspen CO
Leslie D. Kohn - Fremont CA
Charles E. Narad - Santa Clara CA
Robert Yung - Fremont CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 946
G06F 1324

US Classification:

395741

Abstract:

A virtual I/O processor (VIOP) is implemented using a programmed I/O (PIO) unit. The PIO unit is complemented by a VIOP interrupt, a VIOP interrupt handler, and a number of VIOP data structures. Preferably, the PIO unit is further complemented with a set of dedicated I/O global registers, a number of VIOP library read/write routines for various I/O device types, and non-blocking read and write operations. During execution, these elements cooperate with each other to perform multiple sequences of programmed I/Os as if they were being performed by a dedicated I/O processor.

US Patent:

61287210, Oct 3, 2000

Filed:

Nov 17, 1993

Appl. No.:

8/153814

Inventors:

Robert Yung - Fremont CA
William N. Joy - Aspen CO
Marc Tremblay - Palo Alto CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1500

US Classification:

712 23

Abstract:

A processor method and apparatus. The processor has an execution pipeline, a register file and a controller. The execution pipeline is for executing an instruction and has a first stage for generating a first result and a last stage for generating a final result. The register file is for storing the first result and the final result. The controller makes the first result stored in the register file available in the event that the first result is needed for the execution of a subsequent instruction. By storing the result of the first stage in the register file, the length of the execution pipeline is reduced from that of the prior art. Furthermore, logic required for providing inputs to the execution pipeline is greatly simplified over that required by the prior art.

US Patent:

59387564, Aug 17, 1999

Filed:

Apr 19, 1996

Appl. No.:

8/635350

Inventors:

Timothy J. Van Hook - Menlo Park CA
Leslie Dean Kohn - Fremont CA
Robert Yung - Fremont CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 1500

US Classification:

712 23

Abstract:

The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor and a graphics data alignment address offset. Additionally, the CPU is provided with a graphics execution unit (GRU) for executing a number of graphics operations in accordance to the graphics data scaling factor and alignment address offset, the graphics data having a number of graphics data formats. In one embodiment, the GRU is also used to execute a number of graphics data addition, subtraction, rounding, expansion, merge, alignment, multiplication, logical, compare, and pixel distance operations. The graphics data operations are categorized into a first and a second category, and the GRU concurrently executes one graphics operations from each category. Furthermore, under this embodiment, the IEU is also used to execute a number of graphics data edge handling and 3-D array addressing operations, while the load and store unit (LSU) of the CPU is also used to execute a number of graphics data load and store operations, including conditional store operations.