Roberto S Perez

Address:

3127 Collin Dr, West Palm Bch, FL 33406

VIN:

3VWEF71K07M070678

Make:

VOLKSWAGEN

Model:

JETTA

Year:

2007

Address:

4587 Carthage Cir N, Lake Worth, FL 33463

VIN:

1G1AK15F977339447

Make:

CHEVROLET

Model:

COBALT

Year:

2007

US Patent:

56152175, Mar 25, 1997

Filed:

Dec 1, 1994

Appl. No.:

8/352080

Inventors:

Rick L. Horne - Boynton Beach FL
Terence J. Lohman - Boca Raton FL
Mark G. Noll - Raleigh NC
Jose A. Olive - Miami FL
Roberto V. Perez - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

371 223

Abstract:

A method and apparatus for bypassing a boundary-scan cell during functional operation of an electronic component provides a component output signal (such as a data signal) to a boundary-scan bypass circuit during normal functional operation of the electronic component. The component output signal is multiplexed in the bypass circuit with the test result signal that occurs during boundary-scan testing. During functional operation of the electronic component, the component output signal is selected and provided to an output latch that is clocked by a transition of the clock signal of the electronic component. By bypassing the component output signal around the boundary-scan cell during normal operation, the traversing of the multiplexer by the component output signal after the transition of the clock signal of the component is avoided, thereby reducing off-chip delay.

US Patent:

55554130, Sep 10, 1996

Filed:

Feb 17, 1995

Appl. No.:

8/390610

Inventors:

Terence Lohman - Boca Raton FL
Mark G. Noll - Raleigh NC
Jose A. Olive - Miami FL
Roberto V. Perez - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 946

US Classification:

395733

Abstract:

A computer system that has a processor that services interrupts in response to receipt of a signal at the interrupt request has a first device and a second device coupled to the processor. The first device is capable of transmitting a first interrupt request signal that includes an edge transition. The second device is capable of transmitting a second interrupt request signal that comprises a level assertion. An interrupt handler is coupled to the processor and the first and second devices, the interrupt handler receiving the first and second interrupt request signals as inputs and providing the first and second interrupt request signals as outputs to the processor in a sequence according to a predetermined criteria, the first and second interrupt request signals having identical priority.

US Patent:

56088973, Mar 4, 1997

Filed:

Jun 21, 1996

Appl. No.:

8/667767

Inventors:

Mark G. Noll - Lake Worth FL
Jose A. Olive - Miami FL
Roberto V. Perez - Palm Beach FL
James P. Ward - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 114

US Classification:

395557

Abstract:

A timeout mechanism for a computer system is provided, comprising a clocked linear feedback shift register and a programmable comparing mechanism. The linear feedback shift register comprises a series of latches serially connected to each other, and is responsive to a received interrupt signal to (i) incrementally count sequentially in the presence of the interrupt signal to provide a distinct binary vector array at the outputs of the latches for each count in the sequence and (ii) reset to a particular binary vector array in the absence of the interrupt signal. The comparing mechanism outputs a timeout command in response to the linear feedback shift register reaching a predetermined count and outputting a corresponding predetermined binary vector array at the output of the latches. The timeout mechanism uses a minimal amount of combinatorial logic, while permitting the issuance of a timeout command after the detection of an interrupt signal after any multiple of clock cycles.