Roger N Allen

US Patent:

7663621, Feb 16, 2010

Filed:

Nov 3, 2006

Appl. No.:

11/556515

Inventors:

Roger L. Allen - Lake Oswego OR, US
Harold Robert Zable - Palo Alto CA, US
Robert Ohannessian, Jr. - Austin TX, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 15/00
G06T 15/50
G06T 1/00
G06F 13/14
G09G 5/00

US Classification:

345419, 345426, 345501, 345519, 345582, 345585

Abstract:

Circuits, methods, and apparatus that perform cylindrical wrapping in software without the need for a dedicated hardware circuit. One example performs cylindrical wrapping in software running on shader hardware. In one specific example, the shader hardware is a unified shader that alternately processes geometry, vertex, and fragment information. This unified shader is formed using a number of single-instruction, multiple-data units. Another example provides a method of performing a cylindrical wrap that ensures that a correct texture portion is used for a triangle that is divided by a “seam” of the wrap. To achieve this, primitive vertices are sorted such that results are vertex order invariant. One vertex is selected as a reference. For the other vertices, a difference is found for each coordinate and a corresponding coordinate of the reference vertex.

US Patent:

7809928, Oct 5, 2010

Filed:

Dec 20, 2005

Appl. No.:

11/313872

Inventors:

Roger L. Allen - Lake Oswego OR, US
Brett W. Coon - San Jose CA, US
Ian A. Buck - San Jose CA, US
John R. Nickolls - Los Altos CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 9/30
G06F 17/00
G09G 5/02

US Classification:

712208, 345418, 345589

Abstract:

One embodiment of an instruction decoder includes an instruction parser configured to process a first non-operative instruction and to generate a first event signal corresponding to the first non-operative instruction, and a first event multiplexer configured to receive the first event signal from the instruction parser, to select the first event signal from one or more event signals and to transmit the first event signal to an event logic block. The instruction decoder may be implemented in a multithreaded processing unit, such as a shader unit, and the occurrences of the first event signal may be tracked when one or more threads are executed within the processing unit. The resulting event signal count may provide a designer with a better understanding of the behavior of a program, such as a shader program, executed within the processing unit, thereby facilitating overall processing unit and program design.

US Patent:

7877565, Jan 25, 2011

Filed:

Jan 31, 2006

Appl. No.:

11/344445

Inventors:

Roger L. Allen - Lake Oswego OR, US
Cass W. Everitt - Round Rock TX, US
Henry Packard Moreton - Woodside CA, US
Thomas H. Kong - Los Altos CA, US
Simon S. Moy - Los Altos CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711165, 711E12068, 711E12039, 345537, 345557

Abstract:

Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.

US Patent:

8094158, Jan 10, 2012

Filed:

Jan 31, 2006

Appl. No.:

11/344306

Inventors:

Roger L. Allen - Lake Oswego OR, US
Cass W. Everitt - Round Rock TX, US
Henry P. Moreton - Woodside CA, US
Thomas H. Kong - Los Altos CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

345536, 345535, 345537, 345543, 345545, 718102, 718104, 718105, 711100, 711202, 711206, 711207

Abstract:

Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.

US Patent:

8212824, Jul 3, 2012

Filed:

Dec 19, 2005

Appl. No.:

11/313086

Inventors:

Roger L. Allen - Lake Oswego OR, US
Nitij Mangal - Santa Clara CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 15/16

US Classification:

345502, 345557, 712228

Abstract:

A graphics processing unit includes a first processing controller controlling a first set of multi-threaded processors. A second processing controller controls a second set of multi-threaded processors. A serial bus connects the first processing controller to the second processing controller. The first processing controller gathers first state information from the first set of multi-threaded processors in response to a context switch token and then passes the context switch token over the serial bus to the second processing controller. The second processing controller gathers second state information from the second set of multi-threaded processors in response to the context switch token.

US Patent:

8253748, Aug 28, 2012

Filed:

Nov 29, 2005

Appl. No.:

11/290764

Inventors:

Roger L. Allen - Lake Oswego OR, US
Brett W. Coon - San Jose CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 15/00

US Classification:

345501, 702182

Abstract:

One embodiment of a system for collecting performance data for a multithreaded processing unit includes a plurality of independent performance registers, each configured to count hardware-based and/or software-based events. Functional blocks within the multithreaded processing unit are configured to generate various event signals, and subsets of the events are selected and used to generate one or more functions, each of which increments one of the performance registers. By accessing the contents of the performance registers, a user may observe and characterize the behavior of the different functional blocks within the multithreaded processing unit when one or more threads are executed within the processing unit. The contents of the performance registers may also be used to modify the behavior of the program running on the multithreaded processing unit, to modify a global performance register or to trigger an interrupt.