Roger Martin Jeffery

US Patent:

6459633, Oct 1, 2002

Filed:

Dec 20, 2001

Appl. No.:

10/027129

Inventors:

Roger M. Jeffery - Kempton PA
Peter T. Liu - Allentown PA

Assignee:

Agere Systems Guardian Corp. - Miami Lakes FL

International Classification:

G11C 700

US Classification:

365200, 3652257

Abstract:

An integrated circuit has a plurality of buried metal fuses and an apparatus for selectively controlling the plurality of buried metal fuses. Each buried metal fuse has an output state. A plurality of latches each correspond to a respective one of the plurality of buried metal fuses. An encoding fuse has a first state and a second state. A plurality of gates, consists of either a plurality of XOR gates or a plurality of XNOR gates. Each gate has a first input coupled to the output of a respective one of the plurality of buried metal fuses and a second input coupled to the encoding fuse. Each gate has an output coupled to a respective one of the plurality of latches. Each of the plurality of latches has an output state that is the same as the state of the respective one of the plurality of buried metal fuses to which that latch is coupled, when the encoding fuse is in the first state. Each of the plurality of latches has an output state that is opposite the state of the respective one of the plurality of buried metal fuses to which that latch is coupled, when the encoding fuse is in the second state.

US Patent:

6370074, Apr 9, 2002

Filed:

May 5, 2000

Appl. No.:

09/566099

Inventors:

Roger M. Jeffery - Kempton PA
Peter T. Liu - Allentown PA

Assignee:

Agere Systems Guardian Corp - Allentown PA

International Classification:

G11C 700

US Classification:

3652257, 365200

Abstract:

An integrated circuit has a plurality of buried metal fuses and an apparatus for selectively controlling the plurality of buried metal fuses. Each buried metal fuse has an output state. A plurality of latches each correspond to a respective one of the plurality of buried metal fuses. An encoding fuse has a first state and a second state. A plurality of gates, consists of either a plurality of XOR gates or a plurality of XNOR gates. Each gate has a first input coupled to the output of a respective one of the plurality of buried metal fuses and a second input coupled to the encoding fuse. Each gate has an output coupled to a respective one of the plurality of latches. Each of the plurality of latches has an output state that is the same as the state of the respective one of the plurality of buried metal fuses to which that latch is coupled, when the encoding fuse is in the first state. Each of the plurality of latches has an output state that is opposite the state of the respective one of the plurality of buried metal fuses to which that latch is coupled, when the encoding fuse is in the second state.