Roger R Lee

US Patent:

6294421, Sep 25, 2001

Filed:

Feb 18, 1999

Appl. No.:

9/252314

Inventors:

Fernando Gonzalez - Boise ID
Roger Lee - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218242

US Classification:

438241

Abstract:

Dual gate dielectric constructions and methods therefor are disclosed for different regions on an integrated circuit. In the illustrated embodiment, gate dielectrics in memory array regions of the chip are formed of silicon oxide, while the gate dielectric in the peripheral region comprises a harder material, specifically silicon nitride, and has a lesser overall equivalent oxide thickness. The illustrated peripheral gate dielectric has an oxide-nitride-oxide construction. The disclosed process includes forming silicon nitride over the entire chip followed by selectively etching off the silicon nitride from the memory array region, without requiring a separate mask as compared to conventional processes. After the selective etch, oxide is grown over the entire chip, growing differentially thicker in the memory array region.

US Patent:

6358756, Mar 19, 2002

Filed:

Feb 7, 2001

Appl. No.:

09/777888

Inventors:

Gurtej Sandhu - Boise ID
Roger Lee - Boise ID
Dennis Keller - Boise ID
Trung T. Doan - Boise ID
Max F. Hineman - Boise ID
Ren Earl - Merdian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2100

US Classification:

438 3, 438238, 438381

Abstract:

This invention pertains to a method of fabricating a MRAM structure and the resulting structure. The MRAM structure of the invention has the pinned layer recessed within a trench with the upper magnetic layer positioned over it. The method of MRAM fabrication utilizes a spacer processing technique, whereby the upper magnetic layer of the MRAM stack structure is formed between the region defined by the spacers, thereby allowing for self-alignment of the upper magnetic layer over the underlying pinned magnetic layer.

US Patent:

6391735, May 21, 2002

Filed:

Aug 31, 2000

Appl. No.:

09/653226

Inventors:

D. Mark Durcan - Boise ID
Trung T. Doan - Boise ID
Roger R. Lee - Boise ID
Fernando Gonzalez - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2120

US Classification:

438396, 438387, 438239, 438255

Abstract:

Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (âbottom electrodesâ) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

US Patent:

6395600, May 28, 2002

Filed:

Sep 2, 1999

Appl. No.:

09/389661

Inventors:

D. Mark Durcan - Boise ID
Trung T. Doan - Boise ID
Roger R. Lee - Boise ID
Fernando Gonzalez - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218242

US Classification:

438253, 438254, 438255, 438396, 438397, 438398

Abstract:

Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.

US Patent:

6489244, Dec 3, 2002

Filed:

May 15, 2001

Appl. No.:

09/858290

Inventors:

Roger Lee - Boise ID
Dennis Keller - Boise ID
Ralph Kauffman - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21311

US Classification:

438695, 438712, 257529

Abstract:

A method of making a fuse and a fuse, together with systems and integrated circuits where the fuse provides benefits, are described. A fuse comprising a conductive material is formed on a substrate. A series of dielectric layers having a composite thickness is formed on the substrate and the fuse. The series of dielectric layers serves to insulate a series of conductive layers from each other. The conductive layers are disposed above portions of the substrate. An opening is formed extending through a passivation layer and the series of dielectric layers. The opening exposes a portion of the fuse. Another dielectric layer is formed on the fuse and the fuse may thereafter be programmed by directing a laser beam onto the fuse through the opening.

US Patent:

6498062, Dec 24, 2002

Filed:

Apr 27, 2001

Appl. No.:

09/842788

Inventors:

D. Mark Durcan - Boise ID
Roger Lee - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218242

US Classification:

438246, 257302

Abstract:

A method of forming memory devices, such as DRAM access transistors, having recessed gate structures is disclose. Field oxide areas for isolation are first formed over a semiconductor substrate subsequent to which transistor grooves are patterned and etched in a silicon nitride layer. The field oxide areas adjacent to the transistor grooves are then recessed, so that subsequently deposited polysilicon for gate structure formation can be polished relative to the adjacent and elevated silicon nitride.

US Patent:

6521931, Feb 18, 2003

Filed:

Jan 9, 2002

Appl. No.:

10/040447

Inventors:

Gurtej Sandhu - Boise ID
Roger Lee - Boise ID
Dennis Keller - Boise ID
Trung T. Doan - Boise ID
Max F. Hineman - Boise ID
Ren Earl - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2976

US Classification:

257295, 257421

Abstract:

A method of fabricating a MRAM structure and the resulting structure. The MRAM structure of the invention has the pinned layer recessed within a trench with the upper magnetic layer positioned over it. The method of MRAM fabrication utilizes a spacer processing technique, whereby the upper magnetic layer of the MRAM stack structure is formed between the region defined by the spacers, thereby allowing for self-alignment of the upper magnetic layer over the underlying pinned magnetic layer.

US Patent:

6528834, Mar 4, 2003

Filed:

Aug 31, 2000

Appl. No.:

09/653005

Inventors:

D. Mark Durcan - Boise ID
Trung T. Doan - Boise ID
Roger R. Lee - Boise ID
Fernando Gonzalez - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 27108

US Classification:

257296, 257303, 257306, 257307, 257308, 257309, 438381, 438382, 438383, 438384, 438385

Abstract:

Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (âbottom electrodesâ) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.