Rohith Sood from 4135 15Th Ave, Portland, OR 97211, age 49, Phone: (503)3312508

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Location:

Portland, OR

Industry:

Semiconductors

Work:

Lattice Semiconductor since Aug 2011
Senior Test Development Engineer
Lattice Semiconductor May 1997 - Jul 2011
Senior Design Engineer

Education:

University of Washington 1992 - 1997
BS, Electrical Engineering

Skills:

Asic
Cmos
Semiconductors
Ic
Mixed Signal
Soc
Debugging
Analog
Eda
Fpga
Circuit Design
Verilog
Lvs
Drc
Floorplanning

Triggered Sense Amplifier
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US Patent:

8477549, Jul 2, 2013
Filed:

Dec 22, 2010
Appl. No.:

12/976520
Inventors:

Rohith Sood - Portland OR, US
Zheng Chen - Upper Macungie PA, US
Loren McLaury - Hillsboro OR, US
Assignee:

Lattice Semiconductor Corporation - Hillsboro OR
International Classification:

G11C 7/00
US Classification:

365203, 365154, 365156, 326 38, 326 47
Abstract:

Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a programmable logic device (PLD) includes a plurality of static random access memory (SRAM) cells adapted to configure the PLD for an intended use. A pair of bitlines are connected to the SRAM cells. At least one of the SRAM cells is adapted to provide data signals to the bitlines in response to a wordline signal received by the one of the SRAM cells during a read operation. A sense amplifier is connected to the bitlines and adapted to detect a data value from the data signals in response to a trigger signal received by the sense amplifier during the read operation. Logic is adapted to delay the trigger signal relative to the wordline signal to permit the data signals to settle before the sense amplifier detects the data value.

Blocking Memory Readback In A Programmable Logic Device
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US Patent:

8522126, Aug 27, 2013
Filed:

Dec 22, 2010
Appl. No.:

12/977011
Inventors:

Zheng Chen - Upper Macungie PA, US
Rohith Sood - Portland OR, US
Loren McLaury - Hillsboro OR, US
Assignee:

Lattice Semiconductor Corporation - Hillsboro OR
International Classification:

G06F 11/10
US Classification:

714807, 714763
Abstract:

A programmable logic device (PLD) is provided that includes: a configuration memory including a plurality of memory cells arranged according to rows and columns, wherein a subset of the rows are RAM rows, and wherein a subset of the columns in each RAM row are RAM columns and at least one column in each RAM row is a flag bit column, the memory cells corresponding to the flag bit column and RAM rows operable to store flag bit signals; a soft error detection (SED) circuit operable to read the configuration memory to derive a checksum; a logic circuit to determine if a RAM row is being read by the SED circuit that includes an asserted flag bit; and a blocking circuit that provides a known logical value to the SED circuit responsive to the logic circuit to block readback of the memory cells corresponding to the RAM rows and RAM columns.

Bitline Floating Circuit For Memory Power Reduction
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US Patent:

8351287, Jan 8, 2013
Filed:

Dec 22, 2010
Appl. No.:

12/976412
Inventors:

Rohith Sood - Portland OR, US
Fabiano Fontana - San Jose CA, US
Zheng Chen - Upper Macungie PA, US
Assignee:

Lattice Semiconductor Corporation - Hillsboro OR
International Classification:

G11C 7/00
US Classification:

365203, 365154, 365156, 326 38, 326 47
Abstract:

Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a memory circuit includes a static random access memory (SRAM) cell. A pair of bitlines are connected to the SRAM cell. A precharge circuit is connected to the bitlines. The precharge circuit is adapted to precharge the bitlines immediately prior to read and write operations performed on the SRAM cell and float relative to the bitlines at other times.

Rohith Sood