Ronald L Bowman

US Patent:

6360806, Mar 26, 2002

Filed:

Apr 5, 2000

Appl. No.:

09/543305

Inventors:

Ronald L. Bowman - Golden CO
Paul G. Swiszcz - Boulder CO

Assignee:

Hunter Douglas Inc. - Upper Saddle River NJ

International Classification:

E06B 936

US Classification:

1601681V, 1601761 V, 1601781 V

Abstract:

A covering for an architectural opening includes a new system for mounting the controls for the covering within the head rail such that suspended vertical vanes are closely positioned relative to the bottom of a head rail and disposed so as to form a continuous and integrated look with the head rail. An improved pantograph is used in the control system with one set of links of the pantograph having tapered side edges to improve stacking of the vanes adjacent to the end of a head rail without sacrificing strength and therefore quality of the control system. An improved operating system in the form of the combination of a tilt wand, coupler and pull cord provides a simplified system for not only moving the vanes along the length of the head rail between extended and retracted positions but for also pivoting the vanes about longitudinal vertical axis between open and closed positions. An improved system for connecting suspended vanes to the control system is also provided with the system being uniquely designed for use with tubular vanes and retains the vanes in a tubular orientation. The tilt wand is connected to the tilt rod within the head rail by an inclined drive connector that enables the tilt wand to be aligned with the pull cord at the location where the pull cord drops from the head rail for manipulation by an operator.

US Patent:

6571851, Jun 3, 2003

Filed:

Oct 13, 2000

Appl. No.:

09/687451

Inventors:

Ralph G. Jelic - Boulder CO
Paul F. Josephson - Longmont CO
Barbara A. Forst Randle - Arvada CO
Jason T. Throne - Steamboat Springs CA
Ronald L. Bowman - Golden CO

Assignee:

Hunter Douglas Inc. - Upper Saddle River NJ

International Classification:

E06B 906

US Classification:

160 8406, 160 87, 160115, 160 90, 160107

Abstract:

Various embodiments of an architectural covering insert primarily adapted for use in simulated divided light openings is disclosed. The insert includes an outer framework with horizontal and vertical dividers, a plurality of horizontally or vertically disposed shade components associated with one or more dividers and control means for moving the shade components between extended and retracted positions across simulated openings defined by the vertical and horizontal dividers. The shade components can be of the roller shade type or collapsible cellular type with the net result being that, from a visual standpoint, there are shade components associated with each individual simulated opening defined by the horizontal and vertical dividers, as opposed to a single shade that covers the entire architectural opening.

US Patent:

6808001, Oct 26, 2004

Filed:

Apr 22, 2003

Appl. No.:

10/421457

Inventors:

Ralph G. Jelic - Boulder CO
Paul F. Josephson - Longmont CO
Barbara A. Forst Randle - Broomfield CO
Jason T. Throne - Steamboat Springs CO
Ronald L. Bowman - Golden CO

Assignee:

Hunter Douglas Inc. - Upper Saddle River NJ

International Classification:

E06B 908

US Classification:

160120

Abstract:

Various embodiments of an architectural covering insert primarily adapted for use in simulated divided light openings is disclosed. The insert includes an outer framework with horizontal and vertical dividers, a plurality of horizontally or vertically disposed shade components associated with one or more dividers and control means for moving the shade components between extended and retracted positions across simulated openings defined by the vertical and horizontal dividers. The shade components can be of the roller shade type or collapsible cellular type with the net result being that, from a visual standpoint, there are shade components associated with each individual simulated opening defined by the horizontal and vertical dividers, as opposed to a single shade that covers the entire architectural opening.

US Patent:

8163624, Apr 24, 2012

Filed:

Jul 30, 2008

Appl. No.:

12/182660

Inventors:

Ronald R. Bowman - Chandler AZ, US

International Classification:

H01L 21/76

US Classification:

438424, 438414

Abstract:

A discrete semiconductor device has a substrate with a first conductivity type of semiconductor material. A first semiconductor layer is formed over the substrate. The first semiconductor layer having the first conductivity type of semiconductor material. A second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second conductivity type of semiconductor material. A trench is formed through the second semiconductor layer and extends into the second semiconductor layer. The trench has a rounded or polygonal shape and vertical sidewalls. The trench is lined with an insulating layer and filled with an insulating material. A boundary between the first and second semiconductor layers forms a p-n junction. The trench surrounds the p-n junction to terminate the electric field of a voltage imposed on the second semiconductor layer. The discrete semiconductor device can also be a transistor, thyristor, triac, or transient voltage suppressor.

US Patent:

20020092877, Jul 18, 2002

Filed:

Jan 16, 2001

Appl. No.:

09/759894

Inventors:

Ronald Bowman - Golden CO, US

International Classification:

B65D035/38

US Classification:

222/490000, 222/175000, 220/714000, 251/342000

Abstract:

A flexible member is fabricated with side walls forming a chamber which is coupled to a liquid source on one side and has a slit through an end wall on the other side. The end wall is generally curved toward the chamber on its interior surface. The exterior surface of the end wall has ridges adjacent to the slit that extends through the end wall. Deformation of the side walls of the flexible member as by biting causes the end wall with the slit to deform and open the slit which otherwise is retained closed by the walls of the flexible member. This action establishes fluid dispensing from the source through the slit. The thickness of the end wall varies over its distance creating weaken areas in the end wall. These weakened areas create areas in which the end wall deforms opening the slit. In addition to the foregoing, the interior surface forming the chamber has a minimal surface area. The surface is smooth, allowing easier cleaning of the chamber.

US Patent:

20100025809, Feb 4, 2010

Filed:

Jul 30, 2008

Appl. No.:

12/182699

Inventors:

Ronald R. Bowman - Chandler AZ, US

Assignee:

TRION TECHNOLOGY, INC. - Tempe AZ

International Classification:

H01L 29/732
H01L 21/331

US Classification:

257526, 438359, 257E29183, 257E21375

Abstract:

An integrated circuit having a substrate with a first conductivity type of semiconductor material. A buried layer is formed in the substrate. The buried layer has a second conductivity type of semiconductor material. A first semiconductor layer is formed over the buried layer. The first semiconductor layer has the second conductivity type of semiconductor material. A trench is formed through the first semiconductor layer and buried layer and extends into the substrate. The trench is lined with an insulating layer and filled with an insulating material. A second semiconductor layer is formed in the first semiconductor layer. The second semiconductor layer has the first conductivity type of semiconductor material. A third semiconductor layer is formed in the second semiconductor layer. The third semiconductor layer has the second conductivity type of semiconductor material. The first, second, and third semiconductor layers form the collector, base, and emitter of a bipolar transistor.

US Patent:

20120175729, Jul 12, 2012

Filed:

Mar 22, 2012

Appl. No.:

13/427543

Inventors:

Ronald R. Bowman - Chandler AZ, US

International Classification:

H01L 29/06

US Classification:

257510, 257E2902

Abstract:

A discrete semiconductor device has a substrate with a first conductivity type of semiconductor material. A first semiconductor layer is formed over the substrate. The first semiconductor layer having the first conductivity type of semiconductor material. A second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second conductivity type of semiconductor material. A trench is formed through the second semiconductor layer and extends into the second semiconductor layer. The trench has a rounded or polygonal shape and vertical sidewalls. The trench is lined with an insulating layer and filled with an insulating material. A boundary between the first and second semiconductor layers forms a p-n junction. The trench surrounds the p-n junction to terminate the electric field of a voltage imposed on the second semiconductor layer. The discrete semiconductor device can also be a transistor, thyristor, triac, or transient voltage suppressor.

US Patent:

20120299148, Nov 29, 2012

Filed:

Aug 7, 2012

Appl. No.:

13/568410

Inventors:

Ronald R. Bowman - Chandler AZ, US

International Classification:

H01L 29/06
H01L 21/762

US Classification:

257510, 438435, 257E21546, 257E2902

Abstract:

An integrated circuit having a substrate with a first conductivity type of semiconductor material. A buried layer is formed in the substrate. The buried layer has a second conductivity type of semiconductor material. A first semiconductor layer is formed over the buried layer. The first semiconductor layer has the second conductivity type of semiconductor material. A trench is formed through the first semiconductor layer and buried layer and extends into the substrate. The trench is lined with an insulating layer and filled with an insulating material. A second semiconductor layer is formed in the first semiconductor layer. The second semiconductor layer has the first conductivity type of semiconductor material. A third semiconductor layer is formed in the second semiconductor layer. The third semiconductor layer has the second conductivity type of semiconductor material. The first, second, and third semiconductor layers form the collector, base, and emitter of a bipolar transistor.