Ronald L Cline

US Patent:

6424567, Jul 23, 2002

Filed:

Jul 7, 1999

Appl. No.:

09/348961

Inventors:

Ronald L. Cline - Albuquerque NM
Bernardo De Oliveira Kastrup Pereira - Eindhoven, NL

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

G11C 1604

US Classification:

36518504, 326 37

Abstract:

A programmable cell comprises an externally loadable electrically erasable (EE) transistor cell that is configured to be independent of the currently active state of the programmed cell. When all of the EE cells are loaded with a new configuration, the contents of all of the EE cells are loaded into the corresponding programmable cells, preferably within one clock cycle. Because the entirety of the programmable cells can be pre-loaded with the new configuration, the time to effect a reconfiguration is one clock cycle. Because an EE cell is significantly smaller than a conventional four to six transistor storage cell, the area required to implement this single-clock-cycle reconfiguration capability is substantially less than traditional dynamically reprogrammable memory configurations. In an alternative embodiment, multiple EE cells can be associated with each programmable cell, thereby allowing a multiple-configuration capability.

US Patent:

6525561, Feb 25, 2003

Filed:

Apr 9, 2001

Appl. No.:

09/829096

Inventors:

Ronald L. Cline - Albuquerque NM

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H03K 191777

US Classification:

326 39

Abstract:

A very fine-grained gate array cell is provided that includes a two-input logic device and a cascade NAND gate with buffered output. The NAND gate accepts a cascade input from another cell, and the cascade output of the NAND gate is provided as a cascade input to the other cell to facilitate the efficient implementation of cross-coupled devices. Each cell contains integral routing paths that facilitate a âsea of cellsâ layout approach. To ease the routing task, the output of each gate array cell is pre-wired so as to facilitate a programmed interconnection to each logic input of adjacent cells, near-adjacent cells, and far cells, and the aforementioned cascade interconnection with adjacent upper and lower cells. This configuration allows adjacent and near-adjacent cells to be easily interconnected to form macro cells that conform to higher level functional blocks. The gate array does not contain explicit routing channels; routing is effected using the prewired routing that is integral with each gate array cell.

US Patent:

6842043, Jan 11, 2005

Filed:

Mar 11, 2003

Appl. No.:

10/386993

Inventors:

Andy T. Nguyen - San Jose CA, US
Ronald L. Cline - Albuquerque NM, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 190175

US Classification:

326 68, 326 70, 326 83

Abstract:

Level shifter circuits that provide fast operation when changing state while generating little crowbar current. Various embodiments are presented that include some of the following features added to conventional level shifters: additional pull-down transistors coupled to each output node and gated by the associated input signal; additional pull-up transistors coupled to each output node or cross-coupled internal node and gated by the associated input signal; additional pull-up transistors coupled to the cross-coupled internal nodes and gated by the opposing output node; and additional pull-down transistors on the output nodes gated by a low voltage power high. Some of these additional transistors allow the input signal to operate more quickly on the output nodes, causing more rapid transitions on the output signals and reducing crowbar current. The pull-downs gated by the low voltage power high ensure that little or no crowbar current occurs during the power-up sequence.

US Patent:

6985019, Jan 10, 2006

Filed:

Apr 13, 2004

Appl. No.:

10/823450

Inventors:

Ping Zhang - Sunnyvale CA, US
Ronald L. Cline - Albuquerque NM, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 5/08

US Classification:

327309

Abstract:

A selectively enabled clamp circuit for limiting voltage overshoot on an input/output (I/O) pin of an associated integrated circuit (IC) device includes a single discharge transistor and a select circuit. The single discharge transistor is connected between the I/O pin and ground potential, and the select circuit is coupled to the I/O pin and includes an input to receive an enable signal and an output coupled to a gate of the signal discharge transistor. For some embodiments, the select circuit includes a level shifter circuit and a voltage detection circuit.

US Patent:

7265586, Sep 4, 2007

Filed:

Feb 25, 2005

Appl. No.:

11/067422

Inventors:

Gubo Huang - Milpitas CA, US
Andy T. Nguyen - San Jose CA, US
Ronald L. Cline - Albuquerque NM, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/0175

US Classification:

326 83, 326 38

Abstract:

A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.

US Patent:

7479805, Jan 20, 2009

Filed:

Aug 1, 2007

Appl. No.:

11/888790

Inventors:

Gubo Huang - Milpitas CA, US
Andy T. Nguyen - San Jose CA, US
Ronald L. Cline - Albuquerque NM, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/0175

US Classification:

326 83, 326 87

Abstract:

A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.

US Patent:

7893712, Feb 22, 2011

Filed:

Sep 10, 2009

Appl. No.:

12/556959

Inventors:

Chin Hua Tan - Sembawang, SG
Shankar Lakka - San Jose CA, US
Ronald L. Cline - Tijeras NM, US
James B. Anderson - Lubbock TX, US
Wayne E. Wennekamp - Rio Rancho NM, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/173

US Classification:

326 41, 326 47, 326113

Abstract:

An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.

US Patent:

8159263, Apr 17, 2012

Filed:

Apr 29, 2010

Appl. No.:

12/770559

Inventors:

Tim Tuan - San Jose CA, US
Ronald L. Cline - Tijeras NM, US
Arifur Rahman - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/173

US Classification:

326 38, 326 40, 326 68

Abstract:

A programmable integrated circuit having a plurality of individually controlled voltage domains. Each voltage domain includes logic circuitry powered by a respective power network. The voltage magnitude of each power network is independently selectable. Each of a plurality of level shifters couples a first and second one of the voltage domains, couples a first port of the logic circuitry of the first voltage domain to a second port of the logic circuitry of the second voltage domain, and shifts from a first signaling protocol of the first port to a second signaling protocol of the second port. The first signaling protocol is referenced to the voltage magnitude of the first voltage domain, and the second signaling protocol is referenced to the voltage magnitude of the second voltage domain. Means are disclosed for controlling the voltage magnitude of the respective power network of one or more of the voltage domains.