Ronald C Green

US Patent:

7057461, Jun 6, 2006

Filed:

Mar 18, 2004

Appl. No.:

10/804974

Inventors:

Alzon B. Canilao - Union City CA, US
Ronald P. Green - Santa Clara CA, US
Gi Young Lee - Saratoga CA, US

Assignee:

Dynalinear Technologies, Inc. - Campbell CA

International Classification:

H03G 3/10

US Classification:

330285, 330296

Abstract:

A power amplifier comprises first and second power transistor stages that receive first and second supply voltages, respectively. First and second bias circuits provide the biasing for the first and second power transistor stages, respectively, in response to a reference voltage and a bias voltage.

US Patent:

7089498, Aug 8, 2006

Filed:

Sep 24, 2001

Appl. No.:

09/962985

Inventors:

Alicemarie G. Rathjen - San Francisco CA, US
Jacquelyn C. Appell Wheeler - Davis CA, US
Ronald M. Green - Norwich VT, US
Xavier Thomas - San Francisco CA, US
Keith A. Dieterich - San Francisco CA, US
John R. Harding - San Francisco CA, US
Lois S. Harding - San Francisco CA, US
William Kimmerly - Agoura Hills CA, US
Jack L. Strauss - Dayton OH, US
Alex Fordyce - Mill Valley CA, US

International Classification:

G06F 3/00
G06F 9/00
G06F 17/00

US Classification:

715741, 345589, 435 6

Abstract:

Method and system for preparing a personal genetic profile includes collecting genetic data from an individual, assigning the data to a coordinate system, storing the data, and providing access for retrieval by the individual from whom the genetic data were collected, after receipt of an Identifier that adequately authenticates the identity of the data requester. Locations of genetic markers are provided as three-dimensional coordinates, described with matrix relationships that are consistent with the primary and secondary chemical structure of molecular constituents of a DNA chain for the individual.

US Patent:

7176043, Feb 13, 2007

Filed:

Dec 16, 2004

Appl. No.:

11/014439

Inventors:

Belgacem Haba - Cupertino CA, US
Masud Beroz - Livermore CA, US
Ronald Green - San Jose CA, US
Ilyas Mohammed - Santa Clara CA, US
Stuart E. Wilson - Menlo Park CA, US
Wael Zohni - San Jose CA, US
Yoichi Kubota - Pleasanton CA, US
Jesse Burl Thompson - Brentwood CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 21/66

US Classification:

438 14, 438 18

Abstract:

A microelectronic package includes a microelectronic element having faces and contacts and a flexible substrate spaced from and overlying a first face of the microelectronic element. The package also includes a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, wherein at least some of the conductive posts are electrically interconnected with the microelectronic element, and a plurality of support elements supporting the flexible substrate over the microelectronic element. The conductive posts are offset from the support elements to facilitate flexure of the substrate and movement of the posts relative to the microelectronic element.

US Patent:

7332799, Feb 19, 2008

Filed:

Dec 28, 2005

Appl. No.:

11/319961

Inventors:

Ronald Green - San Jose CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 23/02
H05K 1/18

US Classification:

257685, 257701, 257702, 257773, 257E23019, 257E2306, 257E23067, 361600, 361762, 361763

Abstract:

A packaged chip is provided which includes a package element on which a signal-bearing conductive trace has an edge laterally adjacent to an edge of a reference conductive trace (e. g. , ground trace) on the same face of a dielectric element, the two traces together functioning as a capacitor. In a particular embodiment, the laterally adjacent traces provide shunt capacitance to compensate for an inductance in a signal path to the chip which includes the signal-bearing conductive trace. In a variation thereof, a transmission line or waveguide is provided which includes the signal-bearing conductive trace and reference trace. In further variations, transmission lines are provided which include one or more metal layers of a package element, separated from each other by a thickness of a dielectric element included in the package element or the air gap between the package and a circuit panel.

US Patent:

7489524, Feb 10, 2009

Filed:

Jun 2, 2005

Appl. No.:

11/143201

Inventors:

Ronald Green - San Jose CA, US
Sridhar Krishnan - Campbell CA, US
Stuart E. Wilson - Menlo Park CA, US
James Gill Shook - Santa Cruz CA, US
Ming Tsai - Sunnyvale CA, US
Andy Stavros - San Jose CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H05K 1/11

US Classification:

361803, 439 44, 439 65, 439 74, 439 85

Abstract:

An assembly is provided which includes a first circuit panel having a top surface, a first dielectric element and first conductive traces disposed on the first dielectric element. In addition, a second circuit panel has a bottom surface, a second dielectric element and second conductive traces disposed on the second dielectric element, where at least a portion of the second circuit panel overlies at least a portion of the first circuit panel. The assembly further includes an interconnect circuit panel having a third dielectric element which has a front surface, a rear surface opposite the front surface, a top end extending between the front and rear surfaces, a bottom end extending between the front and rear surfaces, and a plurality of interconnect traces disposed on the dielectric element. The bottom end of the interconnect element abuts the top surface of the first circuit panel and the top end abuts the bottom surface of the second circuit panel, where at least some of the first conductive traces are in conductive communication with the second conductive traces through the interconnect traces.

US Patent:

7545029, Jun 9, 2009

Filed:

Aug 18, 2006

Appl. No.:

11/506472

Inventors:

Stuart E. Wilson - Menlo Park CA, US
Ronald Green - San Jose CA, US
Richard Dewitt Crisp - Castro Valley CA, US
Giles Humpston - Aylesbury, GB

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 23/02
H05K 7/00
H01L 21/00

US Classification:

257685, 257686, 257701, 257724, 257782, 257E25013, 257E21614, 361777, 361784, 438107, 438109

Abstract:

A stacked microelectronic assembly includes a base substrate having conductive elements projecting from a bottom surface thereof and a first microelectronic subassembly underlying a bottom surface of the base substrate. The first microelectronic subassembly includes a first dielectric substrate, a first microelectronic element connected with the first dielectric substrate and first conductive posts projecting from the first dielectric substrate toward the bottom surface of the base substrate for electrically interconnecting the first microelectronic element and the base substrate. The assembly also has a second microelectronic subassembly overlying the base substrate. The second microelectronic subassembly includes a second dielectric substrate, a second microelectronic element connected with the second dielectric substrate and second conductive posts projecting toward the top surface of the base substrate for electrically interconnecting the second microelectronic element and the base substrate. The first microelectronic subassembly has a first height and the conductive elements projecting from the bottom surface of the base substrate have a second height that is greater than the first height of the first microelectronic subassembly.

US Patent:

7554206, Jun 30, 2009

Filed:

Dec 1, 2006

Appl. No.:

11/607372

Inventors:

Belgacem Haba - Saratoga CA, US
Masud Beroz - Cary NC, US
Ronald Green - San Jose CA, US
Ilyas Mohammed - Santa Clara CA, US
Stuart E. Wilson - Menlo Park CA, US
Wael Zohni - San Jose CA, US
Yoichi Kubota - Pleasanton CA, US
Jesse Burl Thompson - Brentwood CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 23/52
H01L 23/48
H01L 23/40
H01L 23/485
H01L 23/498

US Classification:

257780, 257737, 257738, 257779, 257E23021, 257E23069, 438612, 438613

Abstract:

A microelectronic assembly includes a microelectronic package having a microelectronic element with faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, at least some of the conductive posts being electrically interconnected with the microelectronic element. The package includes a plurality of support elements disposed between the microelectronic element and the substrate and supporting the flexible substrate over the microelectronic element. At least some of the conductive posts are offset from the support elements. The assembly includes a circuitized substrate having conductive pads confronting the conductive posts of the microelectronic package, whereby the conductive posts are electrically interconnected with the conductive pads.

US Patent:

7583165, Sep 1, 2009

Filed:

Dec 28, 2005

Appl. No.:

11/319849

Inventors:

Ronald Green - San Jose CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01P 1/203
H01P 1/20

US Classification:

333202, 333204, 333230

Abstract:

A cavity resonator is provided which includes a shielded enclosure enclosing a volume and a unitary conductor disposed within the volume, the unitary conductor having a first inductor portion and a transmission line portion. The transmission line portion is included in a transmission line having a reference conductor separated from the transmission line portion by a dielectric element. An active semiconductor device is coupled to the unitary conductor, and is operable to conduct a current to the unitary conductor at a resonant frequency of the unitary conductor.