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Ronald T Horan

age ~62

from Carlsbad, CA

Also known as:
  • Ronald Timothy Horan
  • Ronald M Horan
  • Ronald Tr

Ronald Horan Phones & Addresses

  • Carlsbad, CA
  • 110 4Th St, Del Mar, CA 92014
  • 2 Hunnewell Ct, The Woodlands, TX 77382 • (281)2921501 • (281)2921803
  • Spring, TX
  • 3202 Sweet Autumn Cv, Austin, TX 78735 • (512)3479587
  • 2716 Barton Creek Blvd, Austin, TX 78735 • (281)4443284
  • Houston, TX
  • San Antonio, TX
  • Montgomery, TX
  • 2 Hunnewell Way, Spring, TX 77382 • (281)2921803

Work

  • Company:
    Cisco
    Feb 2019
  • Position:
    Director, product management

Education

  • Degree:
    Master of Science, Masters
  • School / High School:
    The University of Texas at San Antonio
    1991 to 1993
  • Specialities:
    Electronics Engineering

Skills

Semiconductors • Go To Market Strategy • Cross Functional Team Leadership • Product Management • Embedded Systems • Ic • Asic

Industries

Semiconductors

Us Patents

  • Apparatus, Method And System For Accelerated Graphics Port Bus Bridges

    view source
  • US Patent:
    6675248, Jan 6, 2004
  • Filed:
    Oct 3, 2000
  • Appl. No.:
    09/678034
  • Inventors:
    Sompong Paul Olarig - Cypress TX
    Usha Rajagopalan - Houston TX
    Ronald Timothy Horan - Houston TX
  • Assignee:
    Hewlett-Packard Development Company, LP. - Houston TX
  • International Classification:
    G06F 1314
  • US Classification:
    710305, 710314, 710306, 710309, 710310
  • Abstract:
    A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth.
  • Apparatus, Method And System For Accelerated Graphics Port Bus Bridges

    view source
  • US Patent:
    20040068602, Apr 8, 2004
  • Filed:
    Oct 6, 2003
  • Appl. No.:
    10/679734
  • Inventors:
    Sompong Olarig - Cypress TX, US
    Usha Rajagopalan - Houston TX, US
    Ronald Horan - Houston TX, US
  • International Classification:
    G06F013/36
  • US Classification:
    710/306000
  • Abstract:
    A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth. Alternate embodiments of the AGP to AGP Bridge can accommodate the single 64-bit AGP bus for increased performance. Another alternate embodiment can accommodate peer-to-peer transfer of data between AGP busses on the bridge.
  • Valid Flag For Disabling Allocation Of Accelerated Graphics Port Memory Space

    view source
  • US Patent:
    59147270, Jun 22, 1999
  • Filed:
    Sep 9, 1997
  • Appl. No.:
    8/925773
  • Inventors:
    Ronald T. Horan - Houston TX
    Phillip M. Jones - Spring TX
    Gregory N. Santos - Cypress TX
    Robert Allan Lester - Houston TX
    Robert C. Elliott - Houston TX
  • Assignee:
    Compaq Computer Corp. - Houston TX
  • International Classification:
    G06F 1516
  • US Classification:
    345503
  • Abstract:
    A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST. An AGP Valid bit is set to indicate whether an AGP device is present or not.
  • Accelerated Graphics Port Programmable Memory Access Arbiter

    view source
  • US Patent:
    60783389, Jun 20, 2000
  • Filed:
    Mar 11, 1998
  • Appl. No.:
    9/038412
  • Inventors:
    Ronald T. Horan - Houston TX
    Phillip M. Jones - Spring TX
    Gregory N. Santos - Cypress TX
    Robert Allan Lester - Houston TX
    Gary J. Piccirillo - Cypress TX
  • Assignee:
    Compaq Computer Corporation - Houston TX
  • International Classification:
    G06F 1316
  • US Classification:
    345521
  • Abstract:
    A computer system having a core logic chipset that interconnects a processor(s), a system memory and peripheral device agents. The core logic chipset has a programmable memory access arbiter that may be programmed to optimize accesses by the computer system processor(s) and agents to the system memory for best computer system performance. The memory access arbiter may be programmed specifically for each system agent. An access count register may be incorporated into the core logic chipset wherein each system agent may be represented by a portion of the access count register. The values programmed into the portions of the access count register determine how many memory accesses the associated agent may take before another agent is granted a memory access, and how many cachelines may be transferred during a memory access.
  • Apparatus, Method And System For Accelerated Graphics Port Bus Bridges

    view source
  • US Patent:
    61674761, Dec 26, 2000
  • Filed:
    Sep 24, 1998
  • Appl. No.:
    9/160280
  • Inventors:
    Sompong Paul Olarig - Cypress TX
    Usha Rajagopalan - Houston TX
    Ronald Timothy Horan - Houston TX
  • Assignee:
    Compaq Computer Corporation - Houston TX
  • International Classification:
    G06F 1338
  • US Classification:
    710128
  • Abstract:
    A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth.
  • Graphics Address Remapping Table Entry Feature Flags For Customizing The Operation Of Memory Pages Associated With An Accelerated Graphics Port Device

    view source
  • US Patent:
    59991984, Dec 7, 1999
  • Filed:
    Sep 9, 1997
  • Appl. No.:
    8/925772
  • Inventors:
    Ronald T. Horan - Houston TX
    Phillip M. Jones - Spring TX
    Gregory N. Santos - Cypress TX
    Robert Allan Lester - Houston TX
    Robert C. Elliott - Houston TX
  • Assignee:
    Compaq Computer Corporation - Houston TX
  • International Classification:
    G06F 1516
  • US Classification:
    345521
  • Abstract:
    A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.
  • Accelerated Graphics Port Memory Mapped Status And Control Registers

    view source
  • US Patent:
    59366400, Aug 10, 1999
  • Filed:
    Sep 30, 1997
  • Appl. No.:
    8/941862
  • Inventors:
    Ronald T. Horan - Houston TX
    Phillip M. Jones - Spring TX
    Gregory N. Santos - Cypress TX
    Robert Allan Lester - Houston TX
    Robert C. Elliott - Houston TX
  • Assignee:
    Compaq Computer Corporation - Houston TX
  • International Classification:
    G06F 1500
    G06F 1206
  • US Classification:
    345501
  • Abstract:
    A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.
  • Apparatus Method And System For 64 Bit Peripheral Component Interconnect Bus Using Accelerated Graphics Port Logic Circuits

    view source
  • US Patent:
    58599894, Jan 12, 1999
  • Filed:
    May 13, 1997
  • Appl. No.:
    8/855341
  • Inventors:
    Sompong Paul Olarig - Cypress TX
    Ronald Timothy Horan - Houston TX
  • Assignee:
    Compaq Computer Corp. - Houston TX
  • International Classification:
    G06T 1300
  • US Classification:
    395309
  • Abstract:
    A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 64 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 64 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 64 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of a PCI device connected to the common bus.

Wikipedia References

Ronald Horan Photo 1

Ronald Horan

About:
Died:

1999

Work:
Position:

Author • President • Linguist • Historian

Education:
Studied at:

Fort Street High School

Area of science:

Secondary education

Specialty:

Translator

Academic degree:

Digital Information Science and Communication

Skills & Activities:
Award:

Recipient of the Medal of the Order of Australia • Prize

Resumes

Ronald Horan Photo 2

Director, Product Management

view source
Location:
167 Acacia Ave, Carlsbad, CA 92008
Industry:
Semiconductors
Work:
Cisco
Director, Product Management

Broadcom Sep 2000 - Sep 2011
Senior Director

Luxtera, Inc. Sep 2000 - Sep 2011
Vice President of Marketing
Education:
The University of Texas at San Antonio 1991 - 1993
Master of Science, Masters, Electronics Engineering
The University of Texas at San Antonio 1982 - 1986
Bachelors, Electrical Engineering
Skills:
Semiconductors
Go To Market Strategy
Cross Functional Team Leadership
Product Management
Embedded Systems
Ic
Asic

Youtube

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Cisco Optics Podcast Ep 17. Silicon photonics...

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Cisco Optics Podcast Ep 18. Silicon photonics...

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Cisco Optics Podcast Ep 16. Silicon photonics...

Silicon photonics was a buzzword in the optics research community for ...

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Cisco Optics Podcast Ep 27. Optics for hypers...

The rise of hyperscale data centers has upended computing and networki...

  • Duration:
    12m 20s

Cisco Optics Podcast Ep 19. Silicon photonics...

Silicon photonics was a buzzword in the optics research community for ...

  • Duration:
    13m 24s

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