Ronald Joseph Kalemba

US Patent:

48191507, Apr 4, 1989

Filed:

Apr 5, 1985

Appl. No.:

6/720573

Inventors:

Andrew T. Jennings - West Chester PA
Joseph S. Schibinger - Phoenixville PA
Ronald J. Kalemba - Berwyn PA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 100

US Classification:

364200

Abstract:

An array of various types of processors for the purpose of simulating computer functions for large computer systems. These functions may vary from simple AND, OR and other functions to large arithmetic logic units and even random access memories. The simulation array is a tree-type array where the leaves of the tree are the actual logic simulation processors with the other processors serving as nodes which route change of value notices among the various logic simulation processors.