- Chicago IL, US Sean M. Ramey - Mill Creek WA, US Ronald James Koontz - Mesa AZ, US Dick P. Wong - Monterey Park CA, US Jackson Chia - San Gabriel CA, US Anthony S. Fornabaio - Scottsdale AZ, US Murali Rangarajan - Chesterfield MO, US Clarke Edgar Moore - Huntsville AL, US David Clyde Sharp - St. Louis MO, US Arnold W. Nordsieck - Bellevue WA, US Paul Eugene Denzel - Bothell WA, US
International Classification:
G06F 1/10 G06F 1/12
Abstract:
A method for synchronizing processor units. An external synchronizer is communicated with to determine whether an undesired amount of skew is present between a first processor unit and a second processor unit in communication with a synchronization system. The first processor unit is selectively directed to perform an action without generating a needed result such that the undesired amount of skew between the first processor unit and the second processor unit is reduced when the undesired amount of skew is present in the first processor unit. The first processor unit and the second processor unit are associated with each other for a high integrity mode in which integrity checks are performed on corresponding messages generated by the first processor unit and the second processor unit.
- Chicago IL, US Sean M. Ramey - Mill Creek WA, US Ronald James Koontz - Mesa AZ, US Dick P. Wong - Monterey Park CA, US Jackson Chia - San Gabriel CA, US Anthony S. Fornabaio - Scottsdale AZ, US Murali Rangarajan - Chesterfield MO, US Clarke Edgar Moore - Huntsville AL, US David Clyde Sharp - St. Louis MO, US Arnold W. Nordsieck - Bellevue WA, US Paul Eugene Denzel - Bothell WA, US
International Classification:
G06F 11/10 G06F 9/54
Abstract:
A method for managing data transfer for a plurality of processors. Transfer messages exchanged between processor units and an external node in an integrity manager located in hardware in communication with the processor units and the external node are received. An exchange of the transfer messages is managed by the processor units with the external node based on a selected mode in mixed integrity modes such that redundantly calculated outputs from the processor units in a high integrity mode match.
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