Ronald Alan Rohrer

US Patent:

7058916, Jun 6, 2006

Filed:

Jun 18, 2002

Appl. No.:

10/174395

Inventors:

Rodney Phelps - Pittsburgh PA, US
Ronald A. Rohrer - Saratoga CA, US
Anthony J. Gadient - Pittsburgh PA, US
Rob A. Rutenbar - Pittsburgh PA, US
L. Richard Carley - Sewickley PA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 11, 716 1, 716 2, 716 4, 716 7, 716 8, 716 16, 716 17

Abstract:

In a method of automatically sizing and biasing a circuit, a database is provided including a plurality of records related to cells that can be utilized to form an integrated circuit. A cell parameter of a cell for a circuit is selected and compared to cell parameters residing in the records stored in the database. One record in the database is selected based upon this comparison and a performance characteristic of the circuit is determined from this record.

US Patent:

7139987, Nov 21, 2006

Filed:

Jul 11, 2003

Appl. No.:

10/618237

Inventors:

Gang Zhang - Pittsburgh PA, US
Enis Aykut Dengi - Tempe AZ, US
Ronald A. Rohrer - Saratoga CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 8, 716 9

Abstract:

In an automated integrated circuit design, if the performances of a layout of circuit devices are not within predetermined tolerances of performance specifications, at least one of the circuit devices is resized or repositioned and an updated value of a device parameter for each resized or repositioned circuit device is determined. A difference between the initial and updated value of each device parameter is then determined and each difference is combined with a ratio formed from changes in the value of one of the device parameters and changes in the value of one of the performances affected by the device parameter. The result of this combination is then combined with the initial value of the performance to determine an updated value therefor.

US Patent:

7213221, May 1, 2007

Filed:

Apr 19, 2004

Appl. No.:

10/827791

Inventors:

Mustafa Celik - Santa Clara CA, US
Ronald A. Rohrer - Saratoga CA, US

Assignee:

Magma Design Automation, Inc. - Santa Clara CA

International Classification:

G06F 9/45
G06F 17/50

US Classification:

716 6, 716 1, 716 3, 716 18, 703 1, 703 2, 703 13

Abstract:

A system and a method are disclosed for performing a timing or signal propagation delay analysis on a circuit. The disclosure includes representing a drive logic stage as a representative linear circuit driven by a current source. The current source is represented as a function of a current at a constant value, a start time, a tail-start time, and a time constant of an equivalent capacitive circuit. Once the current source model is constructed, a logic stage can be analyzed for timing or signal propagation delay using conventional linear circuit analysis techniques. The disclosure also is applicable to resistance capacitance (“RC”) interconnect circuits using a current source model in which an RC load is represented as an effective capacitance and the current source for use in a linear analysis is constructed using an iterative approach.

US Patent:

7412370, Aug 12, 2008

Filed:

Dec 7, 2004

Appl. No.:

11/007521

Inventors:

Richard Trihy - San Jose CA, US
Ronald Alan Rohrer - Saratoga CA, US

Assignee:

Agilent Technologies, Inc. - Santa Clara CA

International Classification:

G06G 7/48
G06F 17/50

US Classification:

703 14, 703 4

Abstract:

The response of linear and non-linear systems to an arbitrary pulse train is modeled for efficient and accurate circuit simulation. First, a harmonic balance analysis is performed for a system incorporating linear and non-linear components. Then, the even and odd frequency components of the harmonic balance result are separated and interpolated. Finally, the resulting interpolated components are combined to generate the frequency domain positive step response and the frequency domain negative step response of the system. These resulting frequency domain step responses are utilized to generate a low order pole/zero model of the step responses. The pole/zero model can then be used to efficiently and accurately model the response of the system to an arbitrary sequence of positive and negative going pulses.

US Patent:

7735048, Jun 8, 2010

Filed:

Nov 24, 2004

Appl. No.:

10/997639

Inventors:

Gang Zhang - Pittsburgh PA, US
Enis Aykut Dengi - Tempe AZ, US
Ronald A. Rohrer - Saratoga CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 18, 703 2

Abstract:

Methods achieve fast parasitic closure in IC (integrated circuit) synthesis flow with particular application to RFIC (radio frequency integrated circuit) synthesis flow. Parasitic corners generated based on earlier layout statistics are incorporated into circuit resizing to enable parasitic robust designs. The worst-case parasitic corners are generated efficiently without expensive statistical computations. A performance-driven placement with simultaneous fast rough routing and device tuning generates high quality placements and compensates for layout induced performance degradations. A regression-tree based macromodeling methodology is introduced for modeling of electrical performances to enable true performance-driven layout synthesis. To improve sampling quality, an annealing-based placer can be used to perform sampling. The modeling methodology can be adapted to include automatically adjusting the device tuning ranges to meet certain model accuracy requirements.