Ronald E Rohrer

US Patent:

53133986, May 17, 1994

Filed:

Jul 23, 1992

Appl. No.:

7/919160

Inventors:

Ronald A. Rohrer - Sewickley PA
Vivek Raghavan - Pittsburgh PA
J. Eric Bracken - Irwin PA

Assignee:

Carnegie Mellon University - Pittsburgh PA

International Classification:

G06F 1520

US Classification:

364468

Abstract:

A method and apparatus for simulating a microelectronic circuit includes the steps of storing of a microelectronic circuit or system representation in a computer system and then dividing the circuit or system into portions containing nonlinear elements and linear partitions. The linear partitions are then independently solved for by modelling each linear partition using Asymptotic Waveform Evaluation (AWE) to form multiport admittance macromodels. These macromodels provide admittance and current stencils, which may be functions of time, to a global MNA matrix used by SPICE at each time point to simulate the operation of the entire microelectronic circuit. A linearized transient representation for the nonlinear elements is provided as SPICE admittance and current stencils using conventional techniques. By using AWE techniques to solve the linear partitions separately, significant savings in computation time and improved computational storage efficiency can be achieved.