Rong Chen

US Patent:

8084087, Dec 27, 2011

Filed:

Feb 14, 2008

Appl. No.:

12/070367

Inventors:

Stacey F. Bent - Stanford CA, US
Rong Chen - Sunnyvale CA, US
Xirong Jiang - Stanford CA, US
Marja N. Mullings - Stanford CA, US
Yuji Saito - Tokyo, JP

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA
Honda Motor Co., Ltd. - Tokyo

International Classification:

C23C 16/00

US Classification:

42725528, 4272481, 42725511

Abstract:

A method of growing spatially-separated and size-controlled particles on substrate surfaces is provided. The method utilizes chemical modification of the substrate surface, an atomic layer deposition (ALD) system, providing a modified layer to the substrate surface and providing an ALD material for nanoparticle deposition. The method induces a Volmer-Weber growth method, where islands of the nanoparticles are formed on the surface. The modified layer controls a number of nucleation sites on the surface, where controlling the number of ALD cycles limits an amount of deposited the material for discrete the nanoparticles. The modified layer can include self-assembled monolayers, modified hydrophobicity of the surface, H-terminated surfaces, and varying functional groups within the modified layer, where thermally attached alkenes, photochemically attached alkenes, thermally attached alkynes or photochemically attached alkynes are attached to the H-terminated surfaces, and the density of the nucleation sites of the nanoparticles are thereby managed.

US Patent:

20080146034, Jun 19, 2008

Filed:

Dec 12, 2007

Appl. No.:

11/954981

Inventors:

MEIHUA SHEN - Fremont CA, US
RONG CHEN - Sunnyvale CA, US
Scott M. Williams - Belmont CA, US

Assignee:

APPLIED MATERIALS, INC. - Santa Clara CA

International Classification:

H01L 21/311

US Classification:

438700, 257E21249

Abstract:

Methods for recess etching are provided herein that advantageously improve lateral to vertical etch ratio requirements, thereby enabling deeper recess etching while maintaining relatively shallow vertical etch depths. Such enhanced lateral etch methods advantageously provide benefits for numerous applications where lateral to vertical etch depth ratios are constrained or where recesses or cavities are desired to be formed. In some embodiments, a method of recess etching includes providing a substrate having a structure formed thereon; forming a recess in the substrate at least partially beneath the structure using a first etch process; forming a selective passivation layer on the substrate; and extending the recess in the substrate using a second etch process. The selective passivation layer is generally formed on regions of the substrate adjacent to the structure but generally not within the recess. The first and second etch processes may be the same or different.

US Patent:

20080286978, Nov 20, 2008

Filed:

May 17, 2007

Appl. No.:

11/749957

Inventors:

Rong Chen - Sunnyvale CA, US
Tae Won Kim - San Jose CA, US
Nicolas Gani - San Jose CA, US
Anisul H. Khan - Santa Clara CA, US

International Classification:

H01L 21/302

US Classification:

438713, 257E21214

Abstract:

An etch method includes etching a masked substrate to form a recess with a first sidewall in the substrate. A thin surface layer of the substrate on the first sidewall is then converted into a passivation layer. The masked substrate is etched again to deepen the recess in the substrate. A surface layer of the substrate on the second sidewall of the recess is then converted into a passivation layer. In one embodiment, upon removal of the passivation layers from both sidewalls, the first and second sidewalls of the high aspect ratio recess are aligned to within 10 Å of each other to provide a high aspect ratio recess having a vertical profile.

US Patent:

20090032880, Feb 5, 2009

Filed:

Aug 3, 2007

Appl. No.:

11/833481

Inventors:

Mark Naoshi Kawaguchi - Sunnyvale CA, US
Meihua Shen - Fremont CA, US
Hiroki Sasano - Sunnyvale CA, US
Rong Chen - Sunnyvale CA, US

International Classification:

H01L 29/94
H01L 21/302
H01L 21/311

US Classification:

257369, 438703, 438710, 257E29345, 257E21214, 257E21246

Abstract:

Methods and apparatuses to etch recesses in a silicon substrate having an isotropic character to undercut a transistor in preparation for a source/drain regrowth. In one embodiment, a cap layer of a first thickness is deposited over a transistor gate stack and spacer structure. The cap layer is then selectively etched in a first region of the substrate, such as a p-MOS region, using a first isotropic plasma etch process and a second anisotropic plasma etch process. In another embodiment, an at least partially isotropic plasma recess etch is performed to provide a recess adjacent to the channel region of the transistor. In a particular embodiment, the plasma etch process provides a recess sidewall that is neither positively sloped nor more than 10 nm re-entrant.

US Patent:

20120165207, Jun 28, 2012

Filed:

Feb 12, 2010

Appl. No.:

13/148458

Inventors:

Atul J. Butte - Stanford CA, US
Rong Chen - Fremont CA, US
Minnie M. Sarwal - Portola Valley CA, US
Tara Sigdel - Palo Alto CA, US

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

G01N 33/566
C40B 30/04

US Classification:

506 9, 435 792, 435 71, 435 721

Abstract:

Methods are provided for monitoring an allograft recipient for a rejection response, e.g., to predict, to diagnose, and/or to characterize a rejection response. In practicing the subject methods, the level of at least one protein in a sample from the allograft recipient, e.g., serum, urine, blood, CSF, tears or saliva, is evaluated, to monitor the subject. Also provided are compositions, systems, and kits that find use in practicing the subject methods.

US Patent:

20130016452, Jan 17, 2013

Filed:

Apr 2, 2010

Appl. No.:

13/637795

Inventors:

Donald S. Gardner - Mountain View CA, US
Eric C. Hannah - Pebble Beach CA, US
Rong Chen - Sunnyvale CA, US
John L. Gustafson - Pleasanton CA, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01G 9/00

US Classification:

361502

Abstract:

In one embodiment a charge storage device includes first () and second () electrically conductive structures separated from each other by a separator (). At least one of the first and second electrically conductive structures includes a porous structure containing multiple channels (). Each one of the channels has an opening () to a surface () of the porous structure. In another embodiment the charge storage device includes multiple nanostructures () and an electrolyte () in physical contact with at least some of the nanostructures. A material () having a dielectric constant of at least 3.9 may be located between the electrolyte and the nanostructures.

US Patent:

20130080068, Mar 28, 2013

Filed:

Apr 13, 2012

Appl. No.:

13/445925

Inventors:

Frederick Dewey - Redwood City CA, US
Euan Ashley - Menlo Park CA, US
Carlos Daniel Bustamante - Emerald Hills CA, US
Atul Butte - Menlo Park CA, US
Jake Byrnes - San Francisco CA, US
Rong Chen - Fremont CA, US

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

G06F 19/12

US Classification:

702 19

Abstract:

An embodiment of the present invention is a methodology for prioritizing variants relevant to inherited Mendelian (“single gene”) disease syndromes according to disease phenotype, gene, and variant level information.

US Patent:

20160268065, Sep 15, 2016

Filed:

May 25, 2016

Appl. No.:

15/163798

Inventors:

- Santa Clara CA, US
Eric C. Hannah - Pebble Beach CA, US
Rong Chen - Sunnyvale CA, US
John L. Gustafson - Pleasanton CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01G 11/86
H01G 11/24
H01G 11/52

Abstract:

In one embodiment a charge storage device includes first () and second () electrically conductive structures separated from each other by a separator (). At least one of the first and second electrically conductive structures includes a porous structure containing multiple channels (). Each one of the channels has an opening () to a surface () of the porous structure. In another embodiment the charge storage device includes multiple nanostructures () and an electrolyte () in physical contact with at least some of the nanostructures. A material () having a dielectric constant of at least 3.9 may be located between the electrolyte and the nanostructures.