Rongchang Yan from 218 Blossom Ct, New Kensington, PA 15068, age 51, Phone: (724)3341983

Resumes

Engineer

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Location:

218 Blossom Ct, New Kensington, PA 15068

Industry:

Electrical/Electronic Manufacturing

Work:

Engineer

Skills:

Fda
Cmc

Us Patents

Technique For Modeling Parasitics From Layout During Circuit Design And For Parasitic Aware Circuit Design Using Modes Of Varying Accuracy
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US Patent:

8261228, Sep 4, 2012
Filed:

Oct 1, 2008
Appl. No.:

12/243394
Inventors:

Prakash Gopalakrishnan - Allison Park PA, US
Rongchang Yan - New Kensington PA, US
Akshat H. Shah - Pittsburgh PA, US
David N. Dixon - Allison Park PA, US
Keith Dennison - Edinburgh, GB
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716136, 716111, 716112, 716115, 703 14
Abstract:

Techniques are presented for accounting for parasitics in the automated design of integrated circuits. In one set of techniques, model values for parasitic models are received on a schematic environment from a user, the parasitic models are evaluated from the schematic using the received model values, the parasitic models are transferred to a layout environment, and the transferred parasitic models are evaluated on the layout environment. In other techniques, model values are received for parasitic models from a user, the parasitic models are evaluated on the layout environment, and the process then backannotates the parasitic models evaluated on the layout environment and corresponding parameter values to a schematic environment. In yet other techniques, a user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.

Technique For Modeling Parasitics From Layout During Circuit Design And For Parasitic Aware Circuit Design Using Modes Of Varying Accuracy
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US Patent:

8584072, Nov 12, 2013
Filed:

Aug 31, 2012
Appl. No.:

13/601757
Inventors:

Prakash Gopalakrishnan - Allison Park PA, US
Rongchang Yan - New Kensington PA, US
Akshat H. Shah - Pittsburgh PA, US
David N. Dixon - Allison Park PA, US
Keith Dennison - Edinburgh, GB
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716132, 716111, 716115, 716136
Abstract:

A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.

Technique For Modeling Parasitics From Layout During Circuit Design And For Parasitic Aware Circuit Design Using Modes Of Varying Accuracy
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US Patent:

8612921, Dec 17, 2013
Filed:

Aug 31, 2012
Appl. No.:

13/601635
Inventors:

Prakash Gopalakrishnan - Allison Park PA, US
Rongchang Yan - New Kensington PA, US
Akshat H. Shah - Pittsburgh PA, US
David N. Dixon - Allison Park PA, US
Keith Dennison - Edinburgh, GB
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716136, 716111, 716112, 716115
Abstract:

A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.

Method And System For Tuning A Circuit
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US Patent:

20080104548, May 1, 2008
Filed:

Oct 12, 2006
Appl. No.:

11/580735
Inventors:

Rongchang Yan - New Kensington PA, US
Prakash Gopalakrishnan - Allison Park PA, US
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 1
Abstract:

The present invention relates to a method and system for tuning a circuit. In one embodiment, the method includes receiving a description of the circuit, and selecting a design point of the circuit for evaluation using a sizing tool, where the design point comprises a design of the circuit that meets a set of predefined design specifications, and the circuit comprises a group of circuit devices. The method further includes receiving a set of tuning information for the group of circuit devices tuning the group of circuit devices using the set of tuning information to create a group of tuned circuit devices, creating an updated layout of the group of tuned circuit devices using a layout tool, creating estimated parasitic information of the group of tuned circuit devices using the updated layout, and verifying the design point meets design goals of the circuit using the estimated parasitic information of the updated layout.