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Rosario J Consiglio

age ~95

from San Jose, CA

Also known as:
  • Rosario Consiglio
  • Joseph Consiglio Rosario
  • Rosario Consiolio
  • Rosario Consiqlio
  • Consiglio Rosario
Phone and address:
6115 Paso Los Cerritos, San Jose, CA 95120

Rosario Consiglio Phones & Addresses

  • 6115 Paso Los Cerritos, San Jose, CA 95120
  • 8224 Allerton Ave, Milwaukee, WI 53220 • (414)3277236
  • Greenfield, WI
  • Mesa, AZ

Work

  • Company:
    Maxim integrated
    Mar 1995 to Jun 2004
  • Position:
    Member of the technical staff

Education

  • School / High School:
    Marquette University

Industries

Semiconductors

Resumes

Rosario Consiglio Photo 1

President And Chief Executive Officer

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Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
Maxim Integrated Mar 1995 - Jun 2004
Member of the Technical Staff

Impulse Semiconductor Mar 1995 - Jun 2004
President and Chief Executive Officer

Lsi Corporation Jan 1990 - Jan 1993
Senior Process Engineer

Amd Oct 1983 - Jan 1990
Device Engineer
Education:
Marquette University
Name / Title
Company / Classification
Phones & Addresses
Rosario Consiglio
President
Impulse Semiconductor Inc
Engineering Services · Nonclassifiable Establishments
1500 Wyatt Dr, Santa Clara, CA 95054
(408)8448436

Us Patents

  • Silicon Controller Rectifier (Scr) With Capacitive Trigger

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  • US Patent:
    56378874, Jun 10, 1997
  • Filed:
    Jun 7, 1995
  • Appl. No.:
    8/475586
  • Inventors:
    Rosario Consiglio - San Jose CA
  • Assignee:
    LSI Logic Corporation - Milpitas CA
  • International Classification:
    H01L 2974
    H02H 700
    H02H 300
  • US Classification:
    257109
  • Abstract:
    A thyristor device includes first and second terminals, a PNPN thyristor structure including first P-region, a first N-region, a second P-region and a second N-region disposed in series between the first and second terminals, and an electrode for inducing an electric field into the second P-region. The induced electric field increases the number of charge carriers in the second P-region, and enables the device to be triggered at a lower voltage applied between the first and second terminals. The electrode includes an insulated gate, and can be connected to either the first or second terminal. The gate can include a thick field oxide layer, or a thin oxide layer to further reduce the triggering voltage. A differentiator including a capacitor connected between the first terminal and the electrode and a resistor connected between the second terminal and the electrode prevents false triggering during normal operation. A metal interconnection layer includes an anode section which is connected to the N-region and to the second terminal, and a cathode section which is connected to the P-region, the first terminal and the electrode, such that the cathode section laterally surrounds the anode section.
  • Electrostatic Discharge Test Structure System And Method

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  • US Patent:
    56752601, Oct 7, 1997
  • Filed:
    Nov 18, 1996
  • Appl. No.:
    8/751567
  • Inventors:
    Rosario J. Consiglio - San Jose CA
  • Assignee:
    LSI Logic Corporation - Milpitas CA
  • International Classification:
    G01R 3128
  • US Classification:
    324763
  • Abstract:
    System and method for optimizing the structure of a transistor to withstand electrostatic discharge by quantitatively evaluating the amount of electrostatic discharge that integrated circuit field effect transistors may endure before material damage results thereto. The system and method utilizes a plurality of test devices, each having certain differences in structure, which are fabricated onto a common integrated circuit substrate for contemporaneous testing of each device under controlled quantitative conditions. The test results may be organized into a "matrix experiment". A matrix experiment is a set of experiments where the settings or values of several product or process parameters to be studied are changed from one experiment to another. An orthogonal matrix array may be utilized to enhance the reliability of the data analysis, and may effectively reduce the number of experiments necessary to establish a reliable conclusion from the limited number of tests performed.
  • Input-Output (I/O) Structure With Capacitively Triggered Thyristor For Electrostatic Discharge (Esd) Protection

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  • US Patent:
    56820470, Oct 28, 1997
  • Filed:
    Jun 7, 1995
  • Appl. No.:
    8/484003
  • Inventors:
    Rosario Consiglio - San Jose CA
    Yen-Hui Ku - Cupertino CA
  • Assignee:
    LSI Logic Corporation - Milpitas CA
  • International Classification:
    H01L 2363
    H01L 2976
    H02H 900
    H02H 322
  • US Classification:
    257335
  • Abstract:
    An input/output structure includes a microelectronic device connected in circuit between a contact pad and a reference potential, and a thyristor device for protecting the microelectronic device from electrostatic discharge. The thyristor device includes first and second terminals connected to the contact pad and to the reference potential respectively, a PNPN thyristor structure including a first P-region, a first N-region, a second P-region and a second N-region disposed in series between the first and second terminals, and an electrode for inducing an electric field into the second P-region. The induced electric field increases the number of charge carriers in the second P-region, and enables the device to be triggered at a lower voltage applied between the first and second terminals. The electrode includes an insulated gate, and can be connected to either the first or second terminal. The gate can include a thick field oxide layer, or a thin oxide layer to further reduce the triggering voltage.
  • Process Tolerant Nmos Transistor For Electrostatic Discharge Protection

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  • US Patent:
    58545042, Dec 29, 1998
  • Filed:
    Apr 1, 1997
  • Appl. No.:
    8/832771
  • Inventors:
    Rosario J. Consiglio - San Jose CA
  • Assignee:
    Maxim Integrated Products, Inc. - Sunnyvale CA
  • International Classification:
    H01L 2976
    H01L 2362
  • US Classification:
    257358
  • Abstract:
    An improved ESD cell provides in the worst case 2,000 volts HBM ESD protection using an NMOS transistor in a lightly-doped drain process. An NMOS transistor has its source connected to ground, and its drain connected through a polysilicon resistor to a pad of an integrated circuit. The pad is also connected by metal to an n+ pocket tap of an n-type epitaxial layer formed on a p-type substrate. The connection of pad metal to the pocket tap forms a second parasitic lateral bipolar junction transistor (BJT) having as a base the p-type well, having an emitter the source of the NMOS transistor, and having as its collector the pocket tap. The parasitic transistor turns on at the right moment and is able to shunt more current around the polysilicon resistor, thus giving a dramatic increase in ESD protection. In a worst case, the ESD cell can pass at a minimum of 2,000 volts, and the expected range of HBM ESD values is between 2,500 volts and 3,000 volts depending upon process variations. Use of a polysilicon resistor allows the device to be driven into avalanche without destroying itself, and enables the parasitic transistor to be turned on.
  • Method For Optimizing The Structure Of A Transistor To Withstand Electrostatic Discharge

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  • US Patent:
    54102545, Apr 25, 1995
  • Filed:
    Mar 4, 1993
  • Appl. No.:
    8/026558
  • Inventors:
    Rosario J. Consiglio - San Jose CA
  • Assignee:
    LSI Logic Corporation - Milpitas CA
  • International Classification:
    G01N 2760
  • US Classification:
    324456
  • Abstract:
    The present invention relates to a system and method of quantitatively evaluating the amount of electrostatic discharge that integrated circuit field effect transistors may endure before material damage results thereto. The system and method utilizes a plurality of test devices, each having certain differences in structure, which are fabricated onto a common integrated circuit substrate for contemporaneous testing of each device under controlled quantitative conditions. The test results may be organized into a "matrix experiment". A matrix experiment comprises a set of experiments where the settings or values of several product or process parameters to be studied are changed from one experiment to another. An orthogonal matrix array may be utilized to enhance the reliability of the data analysis, and may effectively reduce the number of experiments necessary to establish a reliable conclusion from the limited number of tests performed.
  • Integrated Circuit Input/Output Esd Protection Circuit With Gate Voltage Regulation And Parasitic Zener And Junction Diode

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  • US Patent:
    58153608, Sep 29, 1998
  • Filed:
    Dec 6, 1996
  • Appl. No.:
    8/761443
  • Inventors:
    Rosario Consiglio - San Jose CA
    Gina M. Sparacino - Milpitas CA
  • Assignee:
    LSI Logic Corporation - Milpitas CA
  • International Classification:
    H02H 100
  • US Classification:
    361118
  • Abstract:
    An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.
  • Integrated Circuit Input/Output Esd Protection Circuit With Gate Voltage Regulation And Parasitic Zener And Junction Diode

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  • US Patent:
    55946119, Jan 14, 1997
  • Filed:
    Jan 12, 1994
  • Appl. No.:
    8/180741
  • Inventors:
    Rosario Consiglio - San Jose CA
    Gina M. Sparacino - Milpitas CA
  • Assignee:
    LSI Logic Corporation - Milpitas CA
  • International Classification:
    H02H 900
  • US Classification:
    361118
  • Abstract:
    An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.
  • Transmission Line Pulser Discharge Circuit

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  • US Patent:
    58049770, Sep 8, 1998
  • Filed:
    Apr 23, 1997
  • Appl. No.:
    8/838969
  • Inventors:
    Rosario J. Consiglio - San Jose CA
  • International Classification:
    G01R 2726
  • US Classification:
    324678
  • Abstract:
    An RF matching network provides matching between a charged first transmission line and a relay circuit which is switched to connect the charged transmission line to one end of a second transmission line to generate a high-voltage, high-current test pulse for a DUT connected to the other end of the second transmission line. A low pass filter section of the RF matching network suppresses transient and ringing signals which might pass through the parasitic capacitance of the relay circuit and which trigger the prematurely trigger the DUT. To remove residual charge after discharging the first transmission line, the transmission line is grounded with a GND relay before leakage tests are conducted to prevent electrically stress of destruction of leakage testing circuitry if the residual charge is not dissipated before testing for leakage. Termination resistors for the first transmission line are made of material, such as ceramic, that will not change characteristics with high current and will not breakdown in the presence of high electric fields.

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Roisario che si piacchia kn andrea gioia mamma e che calci che volano ...

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    17 Sep, 2008
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Rosario Consiglio Interview by WISN 12 Milwau...

WWII vets, fans prepare for 'Honor Flight' the movie Tribute event Sat...

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In Kitchen with Dean Consiglio

Consiglio comunale Conselve 200912 parte 33by mrfusion001 16 views; 21...

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    Sports
  • Uploaded:
    10 Sep, 2011
  • Duration:
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A MESSAGE TO THE NAVY SEAL COMMANDER IM LOCAT...

BIN LADEN DEATH a HOAX COVERUP for cia's STUXNET VIRUS MELTING DOWN JA...

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  • Uploaded:
    05 Aug, 2012
  • Duration:
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Honor Flight #19 Returns in Time for the Fourth

Baucus Asks Senate to Join Him in Welcoming Montana WWII Veteransby se...

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    Autos & Vehicles
  • Uploaded:
    03 Sep, 2012
  • Duration:
    1m 16s

Classmates

Rosario Consiglio Photo 2

Boys Trade & Tech Hig...

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Graduates:
Richard Zoladkiewicz (1962-1966),
Wayne Schwartz (1965-1969),
Jan John (1971-1975),
Thomas Lemmer (1965-1969),
Rosario Consiglio (1970-1974)

Googleplus

Rosario Consiglio Photo 3

Rosario Consiglio


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