Ross S Heitkamp from 2724 Doverton Sq, Mountain View, CA 94040, age 62, Phone: (650)9612486

Us Patents

Circuit Card Captivation And Ejection Mechanism Including A Lever To Facilitate Removal Of The Mechanism From A Housing
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US Patent:

6406312, Jun 18, 2002
Filed:

Apr 25, 2001
Appl. No.:

09/840981
Inventors:

Ross Suydam Heitkamp - Mountain View CA
Assignee:

Juniper Networks, Inc. - Sunnyvale CA
International Classification:

H01R 1362
US Classification:

439160, 439157, 361754
Abstract:

A removable apparatus for carrying a circuit board includes a carrying plate having a notch to receive a stationary pin of an enclosure and a faceplate connected to one end of the carrying plate. A rotating cam connects to the carrying plate and acts on the pin to move the apparatus relative to the pin during insertion into and removal from the enclosure. The cam includes two different surfaces, each of which acts to move the apparatus either into or out of the enclosure. A linkage is connected to the cam and extends through the faceplate, connecting to a lever on the exterior of the faceplate. The lever is used to rotate the cam, which in conjunction with the pin provides translational motion either to mate a connector on the circuit board with a corresponding connector in the enclosure or to separate the mated connectors, depending on the direction of rotation.

Voltage Sequencing Circuit For Powering-Up Sensitive Electrical Components
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US Patent:

6429706, Aug 6, 2002
Filed:

Oct 24, 2001
Appl. No.:

09/983423
Inventors:

Dilip A. Amin - San Jose CA
Chang Hong Wu - Cupertino CA
Ross Heitkamp - Mountain View CA
Michael Armstrong - Sunnyvale CA
Assignee:

Juniper Networks, Inc. - Sunnyvale CA
International Classification:

H03L 700
US Classification:

327143
Abstract:

A voltage sequencing circuit powers-up electrical systems by sequentially enabling a series of power supply lines to the electrical system. After each power supply line is enabled, the voltage sequencing circuit waits a pre-programmed delay time before enabling the next power supply line. The delay time allows the newly enabled power supply line to settle. Additionally, the voltage sequencing circuit constantly monitors previously enabled power supply lines while continuing to enable the remaining power supply lines. If any of the previously enabled lines fail, the voltage sequencing circuit disables the power supply line before reinitiating a complete power-up sequence.

Multi-Stage Queuing Discipline
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US Patent:

6430191, Aug 6, 2002
Filed:

Jun 30, 1997
Appl. No.:

08/885400
Inventors:

Daniel E. Klausmeier - Sunnyvale CA
Kevin Wong - San Jose CA
Quang Nguyen - San Jose CA
Cherng-Ren Sue - San Jose CA
David A. Hughes - Mountain View CA
Ross Suydam Heitkamp - Mountain View CA
Rafael Gomez - Cupertino CA
Assignee:

Cisco Technology, Inc. - San Jose CA
International Classification:

H04L 1256
US Classification:

370412, 370468
Abstract:

In a digital switch, incoming cells are placed into a queue in a cell memory. The switch maintains various cell queues, including VC queues that correspond to individual connections and QBin queues that correspond to various classes of service. Cells may arrive to a VC queue or a QBin queue but will depart from a QBin queue. Accordingly, cells may be moved from VC queues to QBin queues. Cells are serviced according to the use of QBin Groups. A QBin Group (QBG) includes a number of logical queues (QBins) of cells to be transported in the digital network. After a QBG is selected, one of its logical queues is selected for servicing. The QBG may be selected by examining all of the QBGs to find an eligible QBG which is most overdue for service. A QBin of the selected QBG may then be selected by examining each of the QBins comprising the selected QBG to find the most overdue for service. The QBGs may correspond to virtual interfaces.

Clock Controller For Controlling The Switching To Redundant Clock Signal Without Producing Glitches By Delaying The Redundant Clock Signal To Match A Phase Of Primary Clock Signal
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US Patent:

6675307, Jan 6, 2004
Filed:

Mar 28, 2000
Appl. No.:

09/536886
Inventors:

Ross S. Heitkamp - Mountain View CA
Chang-Hong Wu - Cupertino CA
Assignee:

Juniper Networks, Inc. - Sunnyvale CA
International Classification:

G06F 112
US Classification:

713401, 713503, 327149
Abstract:

A system and method for controlling clocking signals including a clock controller that includes a first input operable to receive a first clock signal having a first frequency, a second input operable to receive a second clock having a same frequency as the first clock signal but of arbitrary phase, a first output and a variable delay line coupling the first clock signal received at the first input to the first output. The first output is operable to couple a delayed version of the first clock signal to the receiving device. The clock controller includes a comparator receiving as an input the first and the second clock signals from the first and second inputs and providing as an output to the variable delay line a control signal for adjusting a delay in the first clock signal so as to match a phase of the second clock signal received at the receiving device.

Hot-Swappable Router Interface Card With Stable Power On/Off Procedure
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US Patent:

6816936, Nov 9, 2004
Filed:

Jan 2, 2001
Appl. No.:

09/751839
Inventors:

Mike M. Wu - Fremont CA
Ross Heitkamp - Mountain View CA
Assignee:

Juniper Networks, Inc. - Sunnyvale CA
International Classification:

G06F 100
US Classification:

710302, 710301, 713340, 713330, 713324
Abstract:

A network router includes hot-swappable physical interface cards that allow the router to communicate using a variety of network technologies. Power to the interface cards is sequentially ramped to avoid disruptive power surges. The router includes multiple power supplies, a power monitor circuit, power on/off control circuitry, and a controller. The controller detects the presence/absence of the physical interface cards and controls the power monitor circuit and power on/off control circuit to sequentially ramp or sequentially remove power to the physical interface cards.

Diagnostic Access To Processors In A Complex Electrical System
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US Patent:

6826713, Nov 30, 2004
Filed:

Jan 2, 2001
Appl. No.:

09/751937
Inventors:

Michael Beesley - Hillsborough CA
Ross Heitkamp - Mountain View CA
Ashok Krishnamurthi - San Jose CA
Kenneth Richard Powell - Palo Alto CA
Assignee:

Juniper Networks, Inc. - Sunnyvale CA
International Classification:

G06F 1100
US Classification:

714 25, 714 48, 713 2
Abstract:

A debugging and diagnostic system allows a developer to receive low-level diagnostic information from multiple processors in a complex electrical system. A bus connects a master processor to the processors to be debugged via corresponding receiver/driver circuits. The receiver/driver circuits receive serial information from the processors and transmit it to the bus. The master processor controls the receiver/driver circuits through a control logic circuit.

Reliable And Redundant Control Signals In A Multi-Master System
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US Patent:

6970961, Nov 29, 2005
Filed:

Jan 2, 2001
Appl. No.:

09/751841
Inventors:

Ross Heitkamp - Mountain View CA, US
Michael Armstrong - Sunnyvale CA, US
Michael Beesley - Hillsborough CA, US
Ashok Krishnamurthi - San Jose CA, US
Kenneth Richard Powell - Palo Alto CA, US
Assignee:

Juniper Networks, Inc. - Sunnyvale CA
International Classification:

G06F013/00
G06F011/00
US Classification:

710110, 714 11
Abstract:

A network device includes redundant buses, redundant master controllers, and slave controllers. Each of the master controllers connects to a corresponding one of the buses. One of the master controllers acts as an active master and the other master controllers act as standby masters. The active master commences a bus cycle that includes an address interval and a data interval, provides a destination address on the corresponding bus during the address interval, and transmits or receives a command or data during the data interval. The slave controllers connect to the bus, detect commencement of the bus cycle, sample the destination address from the bus a predetermined amount of time after commencement of the address interval, and transmit or receive a command or data during the data interval.

Multi-Master And Diverse Serial Bus In A Complex Electrical System
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US Patent:

6981087, Dec 27, 2005
Filed:

Jan 2, 2001
Appl. No.:

09/751449
Inventors:

Ross Heitkamp - Mountain View CA, US
Michael Armstrong - Sunnyvale CA, US
Michael Beesley - Hillsborough CA, US
Ashok Krishnamurthi - San Jose CA, US
Kenneth Richard Powell - Palo Alto CA, US
Mike M. Wu - Fremont CA, US
Assignee:

Juniper Networks, Inc. - Sunnyvale CA
International Classification:

G06F013/00
G06F013/14
G06F013/368
US Classification:

710301, 710300, 710305, 710119
Abstract:

A two wire serial bus is connected between different circuit boards in a complex electrical system. The two wire serial bus may be used to receive status information about each of the circuit boards in the system. A master control processor on one of the circuit boards controls which of the other circuit boards are active on the serial bus. Each of the non-master circuit boards includes a series of switches that electrically isolate or connect portions of the two wire serial bus from one another. Through the series of switches, both the master control processor and processors local to each of the other circuit boards may simultaneously access different portions of the serial bus.