Roya Yaghmai

US Patent:

7815466, Oct 19, 2010

Filed:

Dec 4, 2008

Appl. No.:

12/328752

Inventors:

Roya Yaghmai - Los Angeles CA, US
Frank B. Parrish - Simi Valley CA, US
Daniel DeLessert - Newberg OR, US

Assignee:

Teradyne, Inc. - North Reading MA

International Classification:

H01R 9/05

US Classification:

439581, 439 63, 324754

Abstract:

In one embodiment, an interface module is provided for connecting a plurality of signal paths to a high signal density interface. The interface module includes a board having axial conductor receptacles. The axial conductor receptacles have at least one ground via extending through the board to an interface side of the board and a shield receiving hole in the board extending into the board from a cable side of the board. At least a portion of the at least one ground via being exposed within the shield receiving hole, the shield receiving hole having a plating therein contacting the portion of the at least one ground via exposed within the shield receiving hole. The axial conductor receptacles have a plated center conductor receiving hole in the board, which extends to a signal via. The signal via extends from the center conductor hole to the interface side of the board. A non-plated hole in the board is located between the plated center conductor hole and the shield receiving hole.

US Patent:

7977583, Jul 12, 2011

Filed:

Dec 21, 2007

Appl. No.:

11/963704

Inventors:

Roya Yaghmai - Los Angeles CA, US
Frank B. Parrish - Simi Valley CA, US
Steven Hauptman - Camarillo CA, US

Assignee:

Teradyne, Inc. - North Reading MA

International Classification:

H05K 1/11

US Classification:

174350, 174367, 174377, 174378, 174260, 174261, 174262, 174263, 174264, 361823, 361824, 361825

Abstract:

A shielded cable interface module having cable receiving grooves extending laterally to an edge of the board, each including a center conductor groove, an insulator groove, and a shield groove. A center conductor via and a shield via extend through the board. A conductor plane on the cable termination side surrounds the cable receiving grooves. The conductor plane includes a non-conductor region within the conductor plane adjacent to each of the conductor center conductor grooves. Ground vias associated with the cable receiving grooves are spaced apart from and partially surround the center conductor via outside and adjacent to the non-conductor region, the ground vias extend through the printed circuit board from the cable termination side to the system interface side.

US Patent:

8201328, Jun 19, 2012

Filed:

Dec 4, 2008

Appl. No.:

12/315811

Inventors:

Roya Yaghmai - Los Angeles CA, US
Frank B. Parrish - Simi Valley CA, US
Daniel DeLessert - Newberg OR, US

Assignee:

Tyco Electronics Corporation - Berwyn PA

International Classification:

H01K 3/10
H05K 3/26
H05K 3/10

US Classification:

29852, 29830, 29846

Abstract:

In one implementation, a method is provided for constructing an interface module which includes constructing a board having a signal via through the board, and having at least one ground via extending through the board. The method further includes back drilling the signal via to create a center conductor hole above a remaining portion of the signal via and back drilling a shield opening in the board and at least part way into the at least one ground via such that a height of the center conductor hole is reduced. The method further includes plating the shield opening and the center conductor hole, and back drilling to remove a portion of the plating to electrically isolate the plated shield opening and the plated center conductor hole.

US Patent:

20070007034, Jan 11, 2007

Filed:

Jun 26, 2006

Appl. No.:

11/474921

Inventors:

Arash Behziz - Thousand Oaks CA, US
Roya Yaghmai - Los Angeles CA, US

International Classification:

H05K 1/11
H05K 3/42

US Classification:

174262000, 174264000, 174266000, 029852000

Abstract:

In one embodiment, a laminated printed circuit board translator is provided. In some embodiments, the translator includes a receiving board adapted to receive a pin, the receiving board includes a plated via extending through the receiving board and has a hole for receiving a pin. An interface board laminated with the receiving board has a controlled depth via extending through it to contact a conductive trace. The conductive trace extends between the receiving board and the interface board to connect the plated via of the receiving board with the controlled depth via of the interface board. The controlled depth via is configured so that it is capable of being plated through a single sided drilled opening in the interface board. Some embodiments have a pad on the interface board connected to the controlled depth via.

US Patent:

20190377007, Dec 12, 2019

Filed:

Jun 8, 2018

Appl. No.:

16/003466

Inventors:

- North Reading MA, US
Kevin P. Manning - Thousand Oaks CA, US
Roya Yaghmai - Westlake Village CA, US
Timothy Lee Farris - Moorpark CA, US
Frank Parrish - Simi Valley CA, US

International Classification:

G01R 1/073
G01R 31/28

Abstract:

An example test system has resources that are distributed for access by a device under test (DUT). The example test system includes a device interface board (DIB) having sites to connect to devices to test, and a tester having slots configured to hold test instruments. Each test instrument has resources that are distributed over a dimension of the DIB. The resources are distributed to enable the devices in the sites equal access to the resources.