Rui Li

US Patent:

6472002, Oct 29, 2002

Filed:

Dec 4, 2000

Appl. No.:

09/730415

Inventors:

Xue Wu Liu - Arcadia CA
Tian Xiao Liu - Arcadia CA
Xuewen Liu - Arcadia CA
Rui Li - Arcadia CA

Assignee:

Joe Nieh - City of Industry CA

International Classification:

A23L 1302

US Classification:

426 72, 426 74, 426575, 426615, 426804

Abstract:

A diet food formula for overweight people and diabetics, comprising of agar, carrageenans, alginate, chlorella, spirulina, and water. The diet food formula comprises of all natural materials. The diet food formula cannot be metabolized by the human body after ingestion and will supply the human body with proper nutrients that it requires.

US Patent:

7286953, Oct 23, 2007

Filed:

Feb 21, 2006

Appl. No.:

11/358541

Inventors:

Rui Li - Irvine CA, US
Chirjeev Singh - Tustin CA, US
Ohannes Kuftedjian - Irvine CA, US
Xilin Zhu - Gloucestershire, GB

Assignee:

Mindspeed Technologies, Inc. - Newport Beach CA

International Classification:

G06F 19/00

US Classification:

702123, 702108, 702117, 702119, 702121, 717100, 717110

Abstract:

Various apparatuses, methods, computer programs, and other systems are disclosed for facilitating testing of a module. In embodiment, a method is provided that comprises the steps of creating a plurality of tasks in a computer system, each of the tasks comprising a list of commands that are sent to a plurality of test devices, the test devices comprising the module to be tested and at least one controlled device interfacing with the module during a test of an operation of the module. In addition, the tasks are organized according to a multi-level hierarchy. The tasks are executed according to an order inherent in the multi-level hierarchy, wherein the execution of each task entails communicating the commands of each task to a respective one of the test devices.

US Patent:

20220270938, Aug 25, 2022

Filed:

Feb 19, 2021

Appl. No.:

17/180652

Inventors:

- San Diego CA, US
De LU - San Diego CA, US
Baldeo Sharan SHARMA - Bangalore, IN
Peeyush Kumar PARKAR - Bangalore, IN
Venkat NARAYANAN - San Diego CA, US
Rui LI - San Diego CA, US
Samy Shafik Tawfik ZAYNOUN - San Diego CA, US
Min CHEN - San Diego CA, US
David KIDD - San Diego CA, US
Amit PATIL - Bengaluru, IN

International Classification:

H01L 21/66
G06F 30/398

Abstract:

Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

US Patent:

20190252408, Aug 15, 2019

Filed:

Feb 13, 2018

Appl. No.:

15/895094

Inventors:

- San Diego CA, US
Xiangdong CHEN - San Diego CA, US
Rui LI - San Diego CA, US
Venugopal BOYNAPALLI - San Marcos CA, US

International Classification:

H01L 27/118
H01L 21/768
H01L 27/02

Abstract:

A semiconductor die includes a first diffusion region and a plurality of gates extending across the diffusion region. The plurality of gates are substantially parallel to each other. An interconnect layer above the diffusion region and plurality of gates includes a plurality of signal traces extending in a direction substantially perpendicular to the gates. At least two of the plurality of signal traces are located directly above the diffusion region such that at intersections of two gates with two separate signal traces are in the active transistor region, that is the portion of the gate extending over the diffusion region. Gate contacts coupling the two gates to the two separate signal traces are staggered by coupling to different signal traces.

US Patent:

20190028087, Jan 24, 2019

Filed:

Jan 10, 2018

Appl. No.:

15/867206

Inventors:

- San Diego CA, US
Timothy Donald GATHMAN - San Diego CA, US
Wenbang XU - San Diego CA, US
Li-chung CHANG - Irvine CA, US
Rui LI - San Diego CA, US
Rahul KARMAKER - San Diego CA, US

International Classification:

H03H 11/02

Abstract:

A filter circuit may include a first path having a first complex baseband filter. The circuit may further include a second path having a second complex baseband filter. The circuit may further include a combiner coupled to an output of the first complex baseband filter and an output of the second complex baseband filter.

US Patent:

20180068714, Mar 8, 2018

Filed:

Sep 7, 2016

Appl. No.:

15/258964

Inventors:

- San Diego CA, US
Tony Chung Yiu KWOK - Irvine CA, US
Rui LI - San Diego CA, US
Sei Seung YOON - San Diego CA, US

International Classification:

G11C 11/418
G11C 11/419

Abstract:

A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.

US Patent:

20180046209, Feb 15, 2018

Filed:

Oct 23, 2017

Appl. No.:

15/791226

Inventors:

- San Diego CA, US
Daniel Stasiak - Austin TX, US
Martin Pierre Saint-Laurent - Austin TX, US
Rui Li - San Diego CA, US
Bin Liang - San Diego CA, US
Sei Seung Yoon - San Diego CA, US
Chulmin Jung - San Diego CA, US

International Classification:

G05F 1/10
G06F 1/32
H02M 1/32

Abstract:

A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

US Patent:

20160299517, Oct 13, 2016

Filed:

Apr 10, 2015

Appl. No.:

14/684128

Inventors:

- San Diego CA, US
Daniel Stasiak - Austin TX, US
Martin Pierre Saint-Laurent - Austin TX, US
Rui Li - San Diego CA, US
Bin Liang - San Diego CA, US
Sei Seung Yoon - San Diego CA, US
Chulmin Jung - San Diego CA, US

International Classification:

G05F 1/10

Abstract:

Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.