Russell J Fields

US Patent:

20050059189, Mar 17, 2005

Filed:

Sep 16, 2003

Appl. No.:

10/663948

Inventors:

Rajesh Tiwari - Plano TX, US
Russell Fields - Richardson TX, US
Scott Boddicker - Plano TX, US
Andrew Kim - Plano TX, US

International Classification:

H01L021/44

US Classification:

438118000

Abstract:

A trench is formed in a low K dielectric () over a plurality of vias () also formed in the low K dielectric layer (). The vias are separated by a distance of less than Xand the edge of the trench is greater than Xfrom the edge α of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper (), () to form the interconnect line.

US Patent:

20090121358, May 14, 2009

Filed:

May 12, 2008

Appl. No.:

12/119187

Inventors:

Rajesh Tiwari - Plano TX, US
Russell Fields - Richardson TX, US
Scott A. Boddicker - Plano TX, US
Andrew Tae Kim - Plano TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H01L 23/532
H01L 23/48
H01L 23/522

US Classification:

257758, 257762, 257E23145, 257E23161, 257774

Abstract:

A trench is formed in a low K dielectric () over a plurality of vias () also formed in the low K dielectric layer (). The vias are separated by a distance of less than Xand the edge of the trench is greater than Xfrom the edge α of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper () to form the interconnect line.

US Patent:

20210098565, Apr 1, 2021

Filed:

Sep 26, 2019

Appl. No.:

16/584463

Inventors:

- Dallas TX, US
David Matthew CURRAN - Plano TX, US
Stephen Arlon MEISNER - Allen TX, US
Bhaskar SRINIVASAN - Allen TX, US
Guruvayurappan S. MATHUR - Plano TX, US
Scott William JESSEN - Allen TX, US
Shih Chang CHANG - Allen TX, US
Russell Duane FIELDS - Richardson TX, US
Thomas Terrance LYNCH - Allen TX, US

International Classification:

H01L 49/02

Abstract:

In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.