Ryan Ronald Arch

US Patent:

20200098657, Mar 26, 2020

Filed:

Sep 26, 2018

Appl. No.:

16/143001

Inventors:

Arnab SEN GUPTA - Hillsboro OR, US
Matthew METZ - Portland OR, US
Benjamin CHU-KUNG - Portland OR, US
Abhishek SHARMA - Hillsboro OR, US
Van H. LE - Portland OR, US
Miriam R. RESHOTKO - Portland OR, US
Christopher J. JEZEWSKI - Portland OR, US
Ryan ARCH - Hillsboro OR, US
Ande KITAMURA - Portland OR, US
Jack T. KAVALIEROS - Portland OR, US
Seung Hoon SUNG - Portland OR, US
Lawrence WONG - Beaverton OR, US
Tahir GHANI - Portland OR, US

International Classification:

H01L 23/31
H01L 29/786
H01L 29/45
H01L 29/66
H01L 29/40

Abstract:

Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.

US Patent:

20190348604, Nov 14, 2019

Filed:

May 17, 2019

Appl. No.:

16/414956

Inventors:

- Santa Clara CA, US
RAVI PILLARISETTY - Portland OR, US
PRASHANT MAJHI - San Jose CA, US
UDAY SHAH - Portland OR, US
RYAN E ARCH - Hillsboro OR, US
MARKUS KUHN - Hillsboro OR, US
JUSTIN S. BROCKMAN - Portland OR, US
HUIYING LIU - Portland OR, US
ELIJAH V KARPOV - Portland OR, US
KAAN OGUZ - Portland OR, US
BRIAN S. DOYLE - Portland OR, US
ROBERT S. CHAU - Beaverton OR, US

Assignee:

INTEL CORPORATION - SANTA CLARA CA

International Classification:

H01L 45/00

Abstract:

Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

US Patent:

20180366587, Dec 20, 2018

Filed:

Dec 23, 2015

Appl. No.:

15/777117

Inventors:

- Santa Clara CA, US
Gilbert DEWEY - Hillsboro OR, US
Rafael RIOS - Austin TX, US
Jack T. KAVALIEROS - Portland OR, US
Marko RADOSAVLJEVIC - Portland OR, US
Kent E. MILLARD - Hillsboro OR, US
Marc C. FRENCH - Forest Grove OR, US
Ashish AGRAWAL - Hillsboro OR, US
Benjamin CHU-KUNG - Hillsboro OR, US
Ryan E. ARCH - Hillsboro OR, US

International Classification:

H01L 29/786
H01L 29/06
H01L 29/24
H01L 29/423
H01L 29/49
H01L 21/02
H01L 29/40
H01L 29/66

Abstract:

Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

US Patent:

20180062077, Mar 1, 2018

Filed:

Dec 24, 2014

Appl. No.:

15/529907

Inventors:

NILOY MUKHERJEE - Portland OR, US
RAVI PILLARISETTY - Portland OR, US
PRASHANT MAJHI - San Jose CA, US
UDAY SHAH - Portland OR, US
RYAN E ARCH - Hillsboro OR, US
MARKUS KUHN - Hillsboro OR, US
JUSTIN S. BROCKMAN - Portland OR, US
HUIYING LIU - Portland OR, US
ELIJAH V KARPOV - Portland OR, US
KAAN OGUZ - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 45/00

Abstract:

Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.