Samit R Chaudhuri

US Patent:

7930673, Apr 19, 2011

Filed:

May 28, 2008

Appl. No.:

12/128554

Inventors:

Yunjian (William) Jiang - San Jose CA, US
Arvind Srinivasan - San Jose CA, US
Joy Banerjee - District Burdwan, IN
Yinghua Li - San Jose CA, US
Partha Das - Kolkata, IN
Samit Chaudhuri - Cupertino CA, US

Assignee:

Magma Design Automation, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716132, 716119, 716136, 713500

Abstract:

A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.

US Patent:

7958476, Jun 7, 2011

Filed:

Jul 9, 2008

Appl. No.:

12/170354

Inventors:

Yunjian (William) Jiang - San Jose CA, US
Arvind Srinivasan - San Jose CA, US
Samit Chaudhuri - Cupertino CA, US

Assignee:

Magma Design Automation, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716109, 716101, 713320, 703 15

Abstract:

A power optimization method of deriving gated circuitry in an integrated circuit (IC) is provided. A design description of the IC is received and analyzed. A state machine is identified based on the analysis. One or more candidate blocks are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states of the state machine. A gating circuit is inserted for gating the selected candidate block(s). In another embodiment of power optimization, one or more state machines are identified and a synthesized netlist is generated. One or more candidate blocks in the synthesized netlist are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states in the state machine, and a gating circuit is inserted for gating the selected candidate block(s).

US Patent:

8434047, Apr 30, 2013

Filed:

Jan 25, 2011

Appl. No.:

13/013024

Inventors:

Yunjian (William) Jiang - San Jose CA, US
Arvind Srinivasan - San Jose CA, US
Joy Banerjee - District Burdwan, IN
Yinghua Li - San Jose CA, US
Partha Das - Kolkata, IN
Samit Chaudhuri - Cupertino CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716133, 716109, 716132

Abstract:

A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

US Patent:

20080301594, Dec 4, 2008

Filed:

May 28, 2008

Appl. No.:

12/128574

Inventors:

Yunjian (William) Jiang - San Jose CA, US
Arvind Srinivasan - San Jose CA, US
Joy Banerjee - District Burdwan, IN
Yinghua Li - San Jose CA, US
Partha Das - Kolkata, IN
Samit Chaudhuri - Cupertino CA, US

Assignee:

Magma Design Automation, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 2

Abstract:

A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

US Patent:

20100011324, Jan 14, 2010

Filed:

Jun 5, 2009

Appl. No.:

12/479681

Inventors:

Darren Faulkner - Austin TX, US
Alan Cheuk-Ming Lam - San Jose CA, US
Samit Chaudhuri - Cupertino CA, US
Aditya Shiledar - San Jose CA, US

International Classification:

G06F 17/50

US Classification:

716 2, 716 8, 716 12

Abstract:

Techniques are disclosed for improving bit slice placement and wiring. Some embodiments include swapping cells to improve routing. An alternative embodiment includes copying wiring from a first bit slice to a second bit slice. Another embodiment includes copying blocks or cells from a first bit slice to a second bit slice. Further, the wiring from the first bit slice may be copied to the second bit slice.

US Patent:

20190042941, Feb 7, 2019

Filed:

Aug 3, 2018

Appl. No.:

16/054225

Inventors:

- Campbell CA, US
Peter Ramyalal Suaris - Woodland Hills CA, US
Samit Chaudhuri - Cupertino CA, US

International Classification:

G06N 3/08
G06Q 50/00
G06F 9/30

Abstract:

Techniques are disclosed for reconfigurable fabric operation linkage. A first function to be performed on a reconfigurable fabric is determined, where the first function is performed on a first cluster within the reconfigurable fabric. A distance is calculated from the first cluster to a second cluster that receives output from the first function on the first cluster. A time duration is calculated for the output from the first function to travel to the second cluster. A first set of instructions for the first function is allocated to the first cluster based on the distance and the time duration. The allocating the first set of instructions is accomplished using a satisfiability solver technique including constructing a set of mapping constraints and building a satisfiability model. The satisfiability solver technique includes a Boolean satisfiability problem solving technique. The satisfiability model is solved and a solution is stored.

US Patent:

20180300181, Oct 18, 2018

Filed:

Apr 16, 2018

Appl. No.:

15/953896

Inventors:

- Campbell CA, US
Samit Chaudhuri - Cupertino CA, US

International Classification:

G06F 9/50

Abstract:

Disclosed techniques utilize a satisfiability solver for allocation and/or configuration of resources in a reconfigurable fabric of processing elements. A dataflow graph is an input provided to a toolchain that includes a satisfiability solver. The satisfiability solver operates on subsets of interconnected nodes within a dataflow graph to derive a solution. The solution is trimmed by removing artifacts and unnecessary parts. The solutions of subsets are then used as an input to additional subsets of nodes within the dataflow graph in an iterative process to derive a complete solution. The satisfiability solver technique uses adaptive windowing in both the time dimension and the spatial dimensions of the dataflow graph. Processing elements and routing elements within the reconfigurable fabric are configured based on the complete solution. Data computation is performed based on the dataflow graph using the processing elements and the routing resources.

US Patent:

20180225089, Aug 9, 2018

Filed:

Mar 30, 2018

Appl. No.:

15/941826

Inventors:

- Campbell CA, US
Samit Chaudhuri - Cupertino CA, US

International Classification:

G06F 5/01

Abstract:

An apparatus for mathematical manipulation is described allowing the selective combination of shifters to shift binary numbers of various widths. Selective combination allows on-the-fly adjustment of shifters from independent to coordinated shifting operations. Selective combination allows adjustable hardware-based shifting while saving space and resources. Multiple eight-bit shifters can be configured for a variety of operand widths, such as a 32-bit width, a 24-bit width, a 16-bit width, or an eight-bit width. Multiplexers route the appropriate input data to the appropriate shifters. Bidirectional shifting is configured through a selector tree, including both shift left and shift right operations. Op codes configure the shifters for the desired type of shift and a shifted result is generated.