Samuel J Chu

US Patent:

6357026, Mar 12, 2002

Filed:

Jan 5, 1999

Appl. No.:

09/225950

Inventors:

Tuan M. Hoang - Westminster CA
Samuel Chu - West Hills CA

Assignee:

The Boeing Company - Chicago IL

International Classification:

G01R 3128

US Classification:

714727, 714728, 714732

Abstract:

A system and method for detecting speed related defects in an electronic assembly includes application specific integrated circuits (ASICs) designed with registered I/Os to provide true at-speed testing of the electronic assembly. An interconnect test engine and a test access port controller control the generation of a progressive binary patterns. The test engine receives captured data from the other ASICs in response to the binary patterns. The method includes generating binary progressive scan patterns for the output registers of one ASIC that are scanned and captured at the input registers of another ASIC. The test results are stored in a multiple input shift register (MISR) where they can be accessed for examination and diagnostic evaluations.