Samuel J Martin

US Patent:

7096133, Aug 22, 2006

Filed:

May 17, 2005

Appl. No.:

10/908564

Inventors:

Samuel S. Martin - Santa Clara CA, US
Brian R. Baker - Hillister CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

702 77, 324613

Abstract:

A method of establishing a benchmark for a figure of merit indicative of flicker noise of an amplifier circuit.

US Patent:

7892610, Feb 22, 2011

Filed:

May 2, 2008

Appl. No.:

12/114446

Inventors:

J. Wallace Parce - Palo Alto CA, US
James M. Hamilton - Sunnyvale CA, US
Samuel Martin - Cupertino CA, US
Erik Freer - Camptell CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

B05D 1/04

US Classification:

427475, 427458, 427466

Abstract:

Methods and systems for applying nanowires and electrical devices to surfaces are described. In a first aspect, at least one nanowire is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate the at least one nanowire with the electrodes. The electrode pair is aligned with a region of the destination surface. The at least one nanowire is deposited from the electrode pair to the region. In another aspect, a plurality of electrical devices is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate an electrical device of the plurality of electrical devices with the electrodes. The electrode pair is aligned with a region of the destination surface. The electrical device is deposited from the electrode pair to the region.

US Patent:

7968474, Jun 28, 2011

Filed:

Nov 9, 2007

Appl. No.:

11/979949

Inventors:

Samuel Martin - Cupertino CA, US
Xiangfeng Duan - Mountain View CA, US
Katsumasa Fujii - Yamatokoriyama, JP
James M. Hamilton - Sunnyvale CA, US
Hiroshi Iwata - Nara, JP
Francisco Leon - Palo Alto CA, US
Jeffrey Miller - Los Altos Hills CA, US
Tetsu Negishi - Sunnyvale CA, US
Hiroshi Ohki - Tokyo, JP
J. Wallace Parce - Palo Alto CA, US
Paul John Schuele - Washougal WA, US
Akihide Shibata - Santa Clara CA, US
David P. Stumbo - Belmont CA, US
Yasunobu Okada - Gifu, JP

Assignee:

Nanosys, Inc. - Mountain View CA
Sharp Kabushiki Kaisha - Osaka

International Classification:

H01L 21/71

US Classification:

438800, 257E21536, 977883

Abstract:

The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e. g. , an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

US Patent:

8252164, Aug 28, 2012

Filed:

May 23, 2011

Appl. No.:

13/113680

Inventors:

Samuel Martin - Cupertino CA, US
Xiangfeng Duan - Mountain View CA, US
Katsumasa Fujii - Yamatokoriyama, JP
James M. Hamilton - Sunnyvale CA, US
Hiroshi Iwata - Nara, JP
Francisco Leon - Palo Alto CA, US
Jeffrey Miller - Los Altos Hills CA, US
Tetsu Negishi - Sunnyvale CA, US
Hiroshi Ohki - Tokyo, JP
J. Wallace Parce - Palo Alto CA, US
Paul John Schuele - Washougal WA, US
Akihide Shibata - Santa Clara CA, US
David P. Stumbo - Belmont CA, US
Yasunobu Okada - Gifu, JP

Assignee:

Nanosys, Inc. - Palo Alto CA
Sharp Kabushiki Kaisha - Osaka

International Classification:

C25D 13/02

US Classification:

204622, 204477, 977883

Abstract:

The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e. g. , an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

US Patent:

20110165337, Jul 7, 2011

Filed:

Jan 19, 2011

Appl. No.:

13/009675

Inventors:

J. Wallace Parce - Palo Alto CA, US
James M. Hamilton - Sunnyvale CA, US
Samuel Martin - Cupertino CA, US
Erik Freer - Campbell CA, US

Assignee:

NANOSYS, INC. - Palo Alto CA

International Classification:

B05D 1/04
B05B 5/025

US Classification:

427466, 118621, 427475

Abstract:

Methods and systems for applying nanowires and electrical devices to surfaces are described. In a first aspect, at least one nanowire is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate the at least one nanowire with the electrodes. The electrode pair is aligned with a region of the destination surface. The at least one nanowire is deposited from the electrode pair to the region. In another aspect, a plurality of electrical devices is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate an electrical device of the plurality of electrical devices with the electrodes. The electrode pair is aligned with a region of the destination surface. The electrical device is deposited from the electrode pair to the region.

US Patent:

59630973, Oct 5, 1999

Filed:

Jan 27, 1998

Appl. No.:

9/014325

Inventors:

Alexander Viktorovich Garachtchenko - Mountain View CA
Samuel Suresh Martin - Gillette NJ

International Classification:

H03F 304
H03F 316
H03F 345

US Classification:

330310

Abstract:

A low-noise amplifier is disclosed that is capable of amplifying a signal with high gain (e. g. , >60 dB) and low noise (e. g. , 10. sup. 6. OMEGA. ), high common mode rejection and high immunity to external noise sources. An illustrative embodiment of the present invention comprises: a first field-effect transistor having a first lead, a second lead and a third lead; a second field-effect transistor having a first lead, a second lead and a third lead, wherein the first lead of the first field-effect transistor is electrically connected to the first lead of the second field-effect transistor, the second lead of the first field-effect transistor is electrically connected to the second lead of the second field-effect transistor, and the third lead of the first field-effect transistor is electrically connected to the third lead of the second field-effect transistor; and a first bipolar junction transistor having a first lead, a second lead and a third lead, wherein the first lead of the first bipolar junction transistor is electrically connected to the first lead of the first field-effect transistor.

US Patent:

20210297406, Sep 23, 2021

Filed:

Oct 4, 2016

Appl. No.:

15/284947

Inventors:

- San Francisco CA, US
Abhijit Rao - Irvine CA, US
Byron G. Chun - Daly City CA, US
Samuel B. Martin - San Francisco CA, US
Michael H. Chang - Millbrae CA, US
Traci H. Nguyen - San Francisco CA, US
Douglas S. Pelton - Richmond CA, US

International Classification:

H04L 29/06

Abstract:

A system includes at least one hardware processor in communication with a first computing device of a suspect party and a second computing device of an inquiring party, the suspect party being targeted for trust evaluation by the inquiring party, and a memory storing instructions that, when executed by the at least one hardware processor, cause the at least one hardware processor to perform operations. The operations include receiving, from the second computing device, a request to perform a trust evaluation of the suspect party, the request including a permission token, identifying the suspect party based on the permission token, generating a trust result for the suspect party based on financial data associated with the suspect party, the trust result indicating an assessed level of trustworthiness of the suspect party, and transmitting the trust result to the second computing device for display to the inquiring party.

US Patent:

20200380506, Dec 3, 2020

Filed:

Dec 20, 2016

Appl. No.:

15/385187

Inventors:

- San Francisco CA, US
John Chuprevich - Davidson NC, US
Kevin R. Cieslak - Novato CA, US
Christopher P. Clausen - Novato CA, US
Jeffrey A. Cornman - San Francisco CA, US
Bryan Hall - Charlotte NC, US
Julio Jiron - San Bruno CA, US
Bryan Kroll - San Mateo CA, US
Samuel Martin - San Francisco CA, US
Traci Nguyen - San Francisco CA, US
Virginia Randle - Tega Cay SC, US
Priyamvada Singh - San Francisco CA, US
Darrell L. Suen - San Ramon CA, US
Kenneth L. Wright - Charlotte NC, US

International Classification:

G06Q 20/40
G06Q 20/10
H04W 12/06
G06F 17/30
H04W 76/02
G06Q 40/02
G06Q 20/32

Abstract:

Systems and methods using a processor coupled to a non-transitory storage medium. The processor is structured to receive an indication of a mobile device connected to a secure network provided by a financial institution, where the mobile device is associated with a user account at the financial institution, identify the mobile device based on a unique identifier of the mobile device, automatically authenticate the mobile device for a first level transaction, receive a transaction request from a user via the mobile device, determine that the transaction request is for the first level transaction, and complete the transaction request.