Samuel S Martin

US Patent:

6938224, Aug 30, 2005

Filed:

Feb 20, 2002

Appl. No.:

10/079447

Inventors:

Thaddeus John Gabara - Murray Hill NJ, US
Samuel Suresh Martin - Gillette NJ, US

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G06F017/50

US Classification:

716 1, 716 4, 716 7, 703 2, 703 14

Abstract:

A method of predicting the electromagnetic noise emitted by a digital circuit on an integrated circuit is disclosed. In accordance with the illustrative embodiment, the output of each digital circuit element in the digital circuit is considered as a bit stream. All of these bits streams are, in aggregate, considered as a noise source that is characterized by a power spectral density, S(ω). The effect of the noise source on an analog circuit can be modeled as a lumped circuit, wherein the lumped circuit contains a noise source that represents the digital circuit; a multi-port network, also referred to as a lumped element, that represents that portion of the substrate between the digital circuit and the analog circuit; and a multi-port network that represents the analog circuit.

US Patent:

7096133, Aug 22, 2006

Filed:

May 17, 2005

Appl. No.:

10/908564

Inventors:

Samuel S. Martin - Santa Clara CA, US
Brian R. Baker - Hillister CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

702 77, 324613

Abstract:

A method of establishing a benchmark for a figure of merit indicative of flicker noise of an amplifier circuit.

US Patent:

7892610, Feb 22, 2011

Filed:

May 2, 2008

Appl. No.:

12/114446

Inventors:

J. Wallace Parce - Palo Alto CA, US
James M. Hamilton - Sunnyvale CA, US
Samuel Martin - Cupertino CA, US
Erik Freer - Camptell CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

B05D 1/04

US Classification:

427475, 427458, 427466

Abstract:

Methods and systems for applying nanowires and electrical devices to surfaces are described. In a first aspect, at least one nanowire is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate the at least one nanowire with the electrodes. The electrode pair is aligned with a region of the destination surface. The at least one nanowire is deposited from the electrode pair to the region. In another aspect, a plurality of electrical devices is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate an electrical device of the plurality of electrical devices with the electrodes. The electrode pair is aligned with a region of the destination surface. The electrical device is deposited from the electrode pair to the region.

US Patent:

7968474, Jun 28, 2011

Filed:

Nov 9, 2007

Appl. No.:

11/979949

Inventors:

Samuel Martin - Cupertino CA, US
Xiangfeng Duan - Mountain View CA, US
Katsumasa Fujii - Yamatokoriyama, JP
James M. Hamilton - Sunnyvale CA, US
Hiroshi Iwata - Nara, JP
Francisco Leon - Palo Alto CA, US
Jeffrey Miller - Los Altos Hills CA, US
Tetsu Negishi - Sunnyvale CA, US
Hiroshi Ohki - Tokyo, JP
J. Wallace Parce - Palo Alto CA, US
Paul John Schuele - Washougal WA, US
Akihide Shibata - Santa Clara CA, US
David P. Stumbo - Belmont CA, US
Yasunobu Okada - Gifu, JP

Assignee:

Nanosys, Inc. - Mountain View CA
Sharp Kabushiki Kaisha - Osaka

International Classification:

H01L 21/71

US Classification:

438800, 257E21536, 977883

Abstract:

The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e. g. , an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

US Patent:

8252164, Aug 28, 2012

Filed:

May 23, 2011

Appl. No.:

13/113680

Inventors:

Samuel Martin - Cupertino CA, US
Xiangfeng Duan - Mountain View CA, US
Katsumasa Fujii - Yamatokoriyama, JP
James M. Hamilton - Sunnyvale CA, US
Hiroshi Iwata - Nara, JP
Francisco Leon - Palo Alto CA, US
Jeffrey Miller - Los Altos Hills CA, US
Tetsu Negishi - Sunnyvale CA, US
Hiroshi Ohki - Tokyo, JP
J. Wallace Parce - Palo Alto CA, US
Paul John Schuele - Washougal WA, US
Akihide Shibata - Santa Clara CA, US
David P. Stumbo - Belmont CA, US
Yasunobu Okada - Gifu, JP

Assignee:

Nanosys, Inc. - Palo Alto CA
Sharp Kabushiki Kaisha - Osaka

International Classification:

C25D 13/02

US Classification:

204622, 204477, 977883

Abstract:

The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e. g. , an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

US Patent:

20110165337, Jul 7, 2011

Filed:

Jan 19, 2011

Appl. No.:

13/009675

Inventors:

J. Wallace Parce - Palo Alto CA, US
James M. Hamilton - Sunnyvale CA, US
Samuel Martin - Cupertino CA, US
Erik Freer - Campbell CA, US

Assignee:

NANOSYS, INC. - Palo Alto CA

International Classification:

B05D 1/04
B05B 5/025

US Classification:

427466, 118621, 427475

Abstract:

Methods and systems for applying nanowires and electrical devices to surfaces are described. In a first aspect, at least one nanowire is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate the at least one nanowire with the electrodes. The electrode pair is aligned with a region of the destination surface. The at least one nanowire is deposited from the electrode pair to the region. In another aspect, a plurality of electrical devices is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate an electrical device of the plurality of electrical devices with the electrodes. The electrode pair is aligned with a region of the destination surface. The electrical device is deposited from the electrode pair to the region.

US Patent:

62115413, Apr 3, 2001

Filed:

Feb 2, 1999

Appl. No.:

9/241458

Inventors:

Michael Scott Carroll - Orlando FL
Tony Georgiev Ivanov - Orlando FL
Samuel Suresh Martin - Gillette NJ

Assignee:

Lucent Technologies, Inc. - Murray Hill NJ

International Classification:

H01L 27108
H01L 2976
H01L 31119

US Classification:

257275

Abstract:

An article for de-embedding parasitics and/or acting as an on-wafer calibration standard is disclosed. In particular, some articles in accordance with the present invention provide structures on integrated circuits that mitigate the severity of parasitics Furthermore, some articles in accordance with the present invention are well-suited for use with conductive substrates that operate at high frequencies. In an illustrative embodiment, conductive elements are used to construct structures near and/or around the leads on the integrated circuit. When the structures are grounded, the structures function to (at least) partially shield the leads to and from the DUT in a manner that is analogous to stripline, microstrip and coaxial cable. Because the electric fields emanating from the leads terminate in the grounded structure and not in the conductive substrate of the integrated circuit, the severity of the parasitics in the leads in mitigated. An illustrative embodiment of the present invention is an integrated circuit comprising: a first pad, a first lead, a second pad, and a second lead made from a first conductive layer; a substrate; a first plate made from a second conductive layer that is between and electrically insulated from the first lead and the substrate; and a second plate made from the second conductive layer that is between and electrically insulated from the second lead and the substrate.

US Patent:

56839170, Nov 4, 1997

Filed:

Jul 3, 1996

Appl. No.:

8/674956

Inventors:

Samuel Suresh Martin - Gillette NJ
Ralph Francis Trambarulo - Red Bank NJ
Cuong Tran - Howell NJ

Assignee:

Lucent Technologies - Murray Hill NJ

International Classification:

H01L 2166

US Classification:

437 8

Abstract:

The disclosed method of making a semiconductor device comprises a screening procedure that facilitates identification of devices having relatively low flicker noise. The devices are typically semiconductor diodes. The procedure utilizes our discovery of a correlation between the reverse bias current I. sub. r of a semiconductor device and the flicker noise power, and comprises measurement of the reverse bias current and comparison of the measured value with a predetermined comparison value I. sub. rc. Devices having I. sub. r. ltoreq. I. sub. rc are those that have relatively low flicker noise. The screening procedure is simple and quick, and can be readily performed in a manufacturing environment.