Samuel E Ray

US Patent:

7812643, Oct 12, 2010

Filed:

Feb 5, 2009

Appl. No.:

12/366005

Inventors:

Shashikala Govindu - Union City CA, US
Samuel Taylor Ray - Morgan Hill CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19/20
H03K 19/094

US Classification:

326115, 327108

Abstract:

A method and current mode logic (CML) multiplexer circuit for implementing load balancing, and a design structure on which the subject circuit resides are provided. CML multiplexer circuit includes first and second differential transistor pairs receiving a first differential input signal and a second differential input signal. The respective transistors of the first and second differential transistor pairs are connected to respective differential signal first and second outputs. CML multiplexer circuit includes load balancing third and fourth differential transistor pairs receiving the first differential input signal and the second differential input signal. The respective transistors of the load balancing third and fourth differential transistor pairs are connected to the opposite differential signal outputs as the first and second differential transistor pairs and the select devices are turned off, matching the source impedance of the unselected first or second differential transistor pair.