Santhosh H Srinath

age ~42

from Menlo Park, CA

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Also known as:

Srinath Santhosh
Santosh Sirnath

Phone and address:: 311 Homewood Pl, Menlo Park, CA 94025

Connected to:

Santhosh Srinath Phones & Addresses

311 Homewood Pl, Menlo Park, CA 94025
12100 Metric Blvd, Austin, TX 78758
Kirkland, WA
Portland, OR
Hillsboro, OR
Ames, IA

Work

Company:

Intel corporation
Aug 1, 2015
Position:

Research scientist

Skills

Processors • Computer Architecture • Microprocessors • Gpu • Simulations • Architecture • Microarchtecture • Gpu Architecture • Performance Simulation • Hardware/Software Codesign • Cpu Architecture • Parallel Programming • Performance Tuning • Complex Software Development • Team Building • Team Leadership • Technology Evaluation

Languages

English

Industries

Computer Hardware

Resumes

Research Scientist

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Location:

311 Homewood Pl, Menlo Park, CA 94025

Industry:

Computer Hardware

Work:

Intel Corporation
Research Scientist

Skills:

Processors
Computer Architecture
Microprocessors
Gpu
Simulations
Architecture
Microarchtecture
Gpu Architecture
Performance Simulation
Hardware/Software Codesign
Cpu Architecture
Parallel Programming
Performance Tuning
Complex Software Development
Team Building
Team Leadership
Technology Evaluation

Languages:

English

Name / Title

Company / Classification

Phones & Addresses

Santhosh Srinath
Owner, Director, Founder

BLUECRYSTALS, LLC

2016 Goodrich Ave UNIT 2A, Austin, TX 78704

Us Patents

Providing Quality Of Service Via Thread Priority In A Hyper-Threaded Microprocessor
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US Patent:

20090049446, Feb 19, 2009
Filed:

Aug 14, 2007
Appl. No.:

11/838458
Inventors:

Matthew Merten - Hillsboro OR, US
Santhosh Srinath - Kirkland WA, US
Morris Marden - Hillsboro OR, US
John Holm - Beaverton OR, US
Glenn Hinton - Portland OR, US
International Classification:

G06F 9/46
US Classification:

718103
Abstract:

A method and apparatus for providing quality of service in a multi-processing element environment based on priority is herein described. Consumption of resources, such as a reservation station and a pipeline, are biased towards a higher priority processing element. In a reservation station, mask elements are set to provide access for higher priority processing elements to more reservation entries. In a pipeline, bias logic provides a ratio of preference for selection of a high priority processing

Scalable Toggle Point Control Circuitry For A Clustered Decode Pipeline
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US Patent:

20230099989, Mar 30, 2023
Filed:

Sep 24, 2021
Appl. No.:

17/484969
Inventors:

- Santa Clara CA, US
Jonathan Combs - Austin TX, US
Martin J. Licht - Round Rock TX, US
Santhosh Srinath - Menlo Park CA, US
International Classification:

G06F 9/30
G06F 9/38
G06F 11/07
Abstract:

Systems, methods, and apparatuses relating to circuitry to implement toggle point insertion for a clustered decode pipeline are described. In one example, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, and a toggle point control circuit to toggle between sending instructions requested for decoding between the first decode cluster and the second decode cluster, wherein the toggle point control circuit is to: determine a location in an instruction stream as a candidate toggle point to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster, track a number of times a characteristic of multiple previous decodes of the instruction stream is present for the location, and cause insertion of a toggle point at the location, based on the number of times, to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster.