Sarah Jane Mcgowan

US Patent:

7015148, Mar 21, 2006

Filed:

May 25, 2004

Appl. No.:

10/852883

Inventors:

Todd P. Lukanc - San Jose CA, US
Luigi Capodieci - Santa Cruz CA, US
Christopher A. Spence - Sunnyvale CA, US
Joerg Reiss - Sunnyvale CA, US
Sarah N. McGowan - San Francisco CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438736, 438720

Abstract:

The invention is a method of manufacturing a semiconductor device and such semiconductor device. The semiconductor device includes an integrated circuit pattern including a horizontal line, a vertical line and a space therebetween, the space including a precise width dimension. The method includes the steps of: forming a photosensitive layer to be patterned, patterning the photosensitive layer to form a pattern including a master horizontal line and a master vertical line without a space therebetween, transferring the pattern to at least one underlying layer using the patterned photosensitive layer, forming a second photosensitive layer over the patterned at least one underlying layer, patterning the second photosensitive layer to form a second pattern including a master space aligned to dissect a horizontal line and a vertical line formed in the at least one underlying layer, and transferring the second pattern to the at least one underlying layer to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a precise width dimension.

US Patent:

7027130, Apr 11, 2006

Filed:

Apr 28, 2004

Appl. No.:

10/833651

Inventors:

Christopher A. Spence - Sunnyvale CA, US
Todd P. Lukanc - San Jose CA, US
Luigi Capodieci - Santa Cruz CA, US
Joerg Reiss - Sunnyvale CA, US
Sarah N. McGowan - San Francisco CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03B 27/72

US Classification:

355 69

Abstract:

A system and method for generating an illumination intensity profile of an illuminator that forms part of a projection lithography system. Radiation from the illuminator is projected towards an illumination profile mask having a plurality of apertures such that each aperture passes a distinct portion of the radiation. The intensity of each of the distinct portions of radiation is detected and assembled to form the illumination intensity profile.

US Patent:

7071085, Jul 4, 2006

Filed:

May 25, 2004

Appl. No.:

10/852876

Inventors:

Todd P. Lukanc - San Jose CA, US
Luigi Capodieci - Santa Cruz CA, US
Christopher A. Spence - Sunnyvale CA, US
Joerg Reiss - Sunnyvale CA, US
Sarah N. McGowan - San Francisco CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/475

US Classification:

438585, 438671, 438736, 438739, 438947

Abstract:

The invention includes an apparatus and a method of manufacturing such apparatus including the steps of: forming a layer to be patterned, forming a photosensitive layer over the layer to be patterned, patterning the photosensitive layer to form a pattern including a horizontal line and a vertical line without a space therebetween, transferring the pattern to the layer to be patterned, forming a second photosensitive layer over the pattern, patterning the second photosensitive layer to form a second pattern including a space aligned between the horizontal line and the vertical line, and transferring the second pattern to the layer to be patterned to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a width dimension achievable at a resolution limit of lithography.

US Patent:

7108946, Sep 19, 2006

Filed:

Jan 12, 2004

Appl. No.:

10/755664

Inventors:

Todd P. Lukanc - San Jose CA, US
Sarah N. McGowan - San Francisco CA, US
Bhanwar Singh - Morgan Hill CA, US
Joerg Reiss - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F 9/00
G03C 5/00

US Classification:

430 22, 430 30, 430312

Abstract:

Methods of fabricating an integrated circuit on a wafer using dual mask exposure lithography is disclosed. Improved mask image alignment between a first mask image and a second mask image of a dual mask exposure technique can be achieved by aligning the second mask image to a latent image created by an exposure using the first mask image.

US Patent:

6995433, Feb 7, 2006

Filed:

Mar 2, 2004

Appl. No.:

10/791250

Inventors:

Todd P. Lukanc - San Jose CA, US
Sarah N. McGowan - San Francisco CA, US
Luigi Capodieci - Santa Cruz CA, US
Bhanwar Singh - Morgan Hill CA, US
Joerg Reiss - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29/94
H01L 31/062

US Classification:

257366, 257401

Abstract:

A microdevice for forming a part of an integrated circuit and method for fabricating are disclosed. The microdevice can include a first conductive region and a second conductive region having a channel region interposed therebetween. The mircodevice has a channel region controlling component disposed over the channel region and separated therefrom by at least one dielectric layer. The channel region controlling component has a non-linear structural characteristic derived from a non-linear structural characteristic of a photo resist feature used as an etch mask for the channel region controlling component.

US Patent:

20140223392, Aug 7, 2014

Filed:

Feb 5, 2013

Appl. No.:

13/759297

Inventors:

- Grand Cayman, KY
Sarah McGowan - San Francisco CA, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

G03F 1/00

US Classification:

716 53

Abstract:

An approach for providing a fragmentation scheme for lithographic fills is provided. In a typical embodiment, a plurality of shapes in a lithographic (e.g., dummy) fill will be grouped/classified into a first set of shapes (e.g., a representative set of shapes) and a second set of shapes (e.g., a similar set of shapes). A set of points will be identified along the edges of the first set of shapes (e.g., at corners of the edges and at positions along the edges that are in alignment with corners of adjacent shapes) to yield an initial mask output. This initial mask output will be copied to the second set of shapes to yield a final mask output which may then be outputted using such an optimized fragmentation scheme.