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Satoshi Mukaida

age ~75

from San Jose, CA

Satoshi Mukaida Phones & Addresses

  • 381 Valley View Ave, San Jose, CA 95127 • (408)2721416
  • Santa Clara, CA
  • 381 Valley View Ave, San Jose, CA 95127

Work

  • Position:
    Professional/Technical

Education

  • Degree:
    High school graduate or higher

Us Patents

  • Signal Timing Adjustment Circuit With External Resistor

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  • US Patent:
    20040008065, Jan 15, 2004
  • Filed:
    Jun 27, 2003
  • Appl. No.:
    10/608747
  • Inventors:
    Dinh Bui - San Jose CA, US
    Paul Self - Santa Clara CA, US
    Pedro Lo - Mountain View CA, US
    Satoshi Mukaida - San Jose CA, US
  • International Classification:
    H03L007/06
  • US Classification:
    327/158000, 327/277000
  • Abstract:
    A semiconductor device includes an external resistor for establishing a delay of a signal relative to another signal in the device. The resistor may be external to a buffer, such as a zero-delay buffer, that receives an input signal generates one or more output signals that relate to the input signal. The delay may be introduced either before or after the buffer.

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