Satya N Yedidi

US Patent:

20130272392, Oct 17, 2013

Filed:

Nov 14, 2011

Appl. No.:

13/994307

Inventors:

Ning Lu - Saratoga CA, US
Hong Jiang - El Dorado Hills CA, US
Atthar H. Mohammed - Folsom CA, US
Satya N. Yedidi - Roseville CA, US

International Classification:

H04N 7/26

US Classification:

37524003

Abstract:

Iterative video encoding systems, methods and computer program products, where residue quantization and data packing operations of an encoding process may he repeated with various values for a quantization parameter, without repeating the determination of macroblock prediction code. In an embodiment, the size of an actual file generated by encoding is compared to a target file size. The QP may be adjusted depending on the amount by which these file sizes differ. The quantization and packing may then be repeated with the adjusted QP. In an embodiment, a greater difference in these file sizes results in a greater adjustment to the QP.

US Patent:

20230097092, Mar 30, 2023

Filed:

Nov 1, 2022

Appl. No.:

17/978290

Inventors:

- Santa Clara CA, US
Satya N. Yedidi - Roseville CA, US
James M. Holland - Folsom CA, US
Dmitry E. Ryzhov - Mountain View CA, US
Jian Hu - El Dorado Hills CA, US
Sai Agnihotri - Newark CA, US
Indira Munagani - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04N 19/124
H04N 19/52
H04N 19/184

Abstract:

Techniques related to video encoding include inline downscaling hardware in multi-pass encoding.

US Patent:

20210374896, Dec 2, 2021

Filed:

Jan 27, 2021

Appl. No.:

17/159708

Inventors:

- Santa Clara CA, US
Stanley J. Baran - Elk Grove CA, US
Sang-Hee Lee - Santa Clara CA, US
Atthar H. Mohammed - Folsom CA, US
Jong Dae Oh - Folsom CA, US
Jill M. Boyce - Portland OR, US
Fangwen Fu - Folsom CA, US
Satya N. Yedidi - Roseville CA, US
Sumit Mohan - San Jose CA, US
James M. Holland - Folsom CA, US
Keith W. Rowe - Shingle Springs CA, US
Altug Koker - El Dorado Hills CA, US

International Classification:

G06T 1/20
G06T 1/60
G09G 5/00
H04N 19/156
G06F 1/3206
G06F 1/3234

Abstract:

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.

US Patent:

20210084294, Mar 18, 2021

Filed:

Nov 30, 2020

Appl. No.:

17/107258

Inventors:

- Santa Clara CA, US
Zhijun Lei - Portland OR, US
Dmitry E. Ryzhov - Mountain View CA, US
Lidong Xu - Beijing, CN
Satya N. Yedidi - Roseville CA, US

International Classification:

H04N 19/11
H04N 19/533
H04N 19/159
H04N 19/176
H04N 19/88
H04N 19/70
H04N 19/593
H04N 19/33
H04N 19/12

Abstract:

Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.

US Patent:

20200359034, Nov 12, 2020

Filed:

Jul 14, 2020

Appl. No.:

16/928747

Inventors:

- Santa Clara CA, US
Fangwen Fu - Folsom CA, US
Satya N. Yedidi - Roseville CA, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H04N 19/176
H04N 19/523
H04N 19/146
H04N 19/103
H04N 19/43

Abstract:

An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder comprises at least a fixed function dual hierarchical motion estimation search units, dual integer motion estimation search units, and a fractional motion estimation search unit. Moreover, the hardware bit packing unit is to pack bits as coded according to the final macroblock coding decision into a data format.

US Patent:

20200186831, Jun 11, 2020

Filed:

Dec 9, 2019

Appl. No.:

16/707485

Inventors:

- Santa Clara CA, US
Sumit Mohan - San Jose CA, US
James M. Holland - Folsom CA, US
Sang-Hee Lee - Santa Clara CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Wen-Fu Kao - West Sacramento CA, US
Joydeep Ray - Folsom CA, US
Ya-Ti Peng - Sunnyvale CA, US
Keith W. Rowe - Shingle Springs CA, US
Fangwen Fu - Folsom CA, US
Satya N. Yedidi - Roseville CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04N 19/593
G06T 11/00
H04N 19/597
H04N 19/136
H04N 19/46
H04N 19/436
H04N 19/105
H04N 19/176
H04N 19/52

Abstract:

An embodiment of an electronic processing system may include a 2D frame which corresponds to a projection of a 360 video space, and a component predictor to predict an encode component for a first block of a 2D frame based on encode information from a neighboring block which is neighboring to the first block of the 2D frame only in the 360 video space, a prioritizer to prioritize transmission for a second block of the 2D frame based on an identified region of interest, and/or a format detector to detect a 360 video format of the 2D frame based on image content. A 360 video capture device may include a contextual tagger to tag 360 video content with contextual information which is contemporaneous with the captured 360 video content. Other embodiments are disclosed and claimed.

US Patent:

20200005424, Jan 2, 2020

Filed:

Jul 18, 2019

Appl. No.:

16/515794

Inventors:

- Santa Clara CA, US
Stanley J. Baran - Elk Grove CA, US
Sang-Hee Lee - Santa Clara CA, US
Atthar H. Mohammed - Folsom CA, US
Jong Dae Oh - Folsom CA, US
Jill M. Boyce - Portland OR, US
Fangwen Fu - Folsom CA, US
Satya N. Yedidi - Roseville CA, US
Sumit Mohan - San Jose CA, US
James M. Holland - Folsom CA, US
Keith W. Rowe - Shingle Springs CA, US
Altug Koker - El Dorado Hills CA, US

International Classification:

G06T 1/20
G06T 1/60
G09G 5/00
H04N 19/156
G06F 1/3206
G06F 1/3234

Abstract:

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.

US Patent:

20190297344, Sep 26, 2019

Filed:

Jun 13, 2019

Appl. No.:

16/440159

Inventors:

- Santa Clara CA, US
Zhijun Lei - Portland OR, US
Dmitry E. Ryzhov - Mountain View CA, US
Lidong Xu - Beijing, CN
Satya N. Yedidi - Roseville CA, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H04N 19/533
H04N 19/159
H04N 19/60
H04N 19/88
H04N 19/70
H04N 19/176

Abstract:

An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.