Saurabh K Singh

US Patent:

20100019841, Jan 28, 2010

Filed:

Jul 22, 2008

Appl. No.:

12/177170

Inventors:

Nitin Agarwal - Bangalore, IN
Saurabh Singh - Austin TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H03F 1/02

US Classification:

330 9

Abstract:

A reference generation circuit provided according to an aspect of the present invention generates a reference potential at different levels in the hold phase of different cycles in an input path of a switched capacitor differential amplifier. In an embodiment, for each hold phase, the reference generator provides the reference potential with a magnitude that tracks the magnitude of the input signal applied in a corresponding (preceding) sample phase. In case of a single-ended output, the reference potential generated for each hold phase equals the magnitude of one of the inputs on the differential input path. As a result, the common mode voltage at the input terminals of an operational amplifier contained in the switched capacitor differential amplifier is maintained at a desired level.

US Patent:

20190379389, Dec 12, 2019

Filed:

Jun 4, 2019

Appl. No.:

16/431276

Inventors:

- Edinburgh, GB
Mark MAY - Austin TX, US
Saurabh SINGH - Cedar Park TX, US
Ramya BALASUNDARAM - Austin TX, US
Mengde WANG - Austin TX, US
Eric B. SMITH - Austin TX, US

Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh

International Classification:

H03M 3/00
H04N 5/232
H03M 1/50
H03M 1/82
H03M 1/12

Abstract:

A system may include an output stage for driving a load at an output of the output stage, a pulse-width modulation mode path configured to pre-drive the output stage in a first mode of operation, a linear mode path configured to pre-drive the output stage in a second mode of operation and a loop filter coupled at its input to the output of the output stage and coupled at its output to both of the pulse-width modulation mode path and the linear mode path. The pulse-width modulation mode path and the linear mode path may be configured such that a first transfer function between the output of the loop filter and the output of the output stage is substantially equivalent to a second transfer function between the output of the loop filter and the output of the output stage

US Patent:

20180212569, Jul 26, 2018

Filed:

Jun 14, 2017

Appl. No.:

15/622722

Inventors:

- Edinburgh, GB
Ku HE - Austin TX, US
Xin ZHAO - Austin TX, US
Miao SONG - Austin TX, US
Saurabh SINGH - Cedar Park TX, US
Vinod JAYAKUMAR - Austin TX, US

Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh

International Classification:

H03F 1/02
H03F 3/217
H03F 3/21
H03F 3/183

Abstract:

A method may include, in an apparatus comprising a closed loop amplifier and a signal processing block configured to generate an amplifier input signal as a function of an upstream signal received at an input of the signal processing block, in a calibration mode of the apparatus: decoupling a second stage input of the amplifier from a first stage output of the amplifier; determining an offset signal that when applied to the input of a signal processing block as the upstream signal generates approximately zero as an intermediate signal generated by the first stage of the amplifier; and controlling one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.

US Patent:

20180046239, Feb 15, 2018

Filed:

Aug 10, 2016

Appl. No.:

15/233624

Inventors:

- Edinburgh, GB
Daniel J. ALLEN - Austin TX, US
Saurabh SINGH - Cedar Park TX, US
Aniruddha SATOSKAR - Austin TX, US

Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh

International Classification:

G06F 1/32
G06F 1/26
H04R 3/04
H03M 1/12

Abstract:

A system may include a plurality of processing paths and a controller. The processing paths may include a first processing path configured to generate a first digital signal based on an analog input signal and one or more other processing paths each configured to consume a smaller amount of power than the first processing path, and each configured to generate a respective digital signal based on the analog input signal, wherein one of the other processing paths has a noise floor based on fidelity characteristics of the analog input signal or subsequent processing requirements of a digital output signal generated from at least one of the first digital signal and the respective digital signals. The controller may be configured to select one of the first digital signal and the respective digital signals as the digital output signal of the processing system based on a magnitude of the analog input signal.

US Patent:

20180048325, Feb 15, 2018

Filed:

Aug 11, 2016

Appl. No.:

15/234741

Inventors:

- Edinburgh, GB
Daniel J. ALLEN - Austin TX, US
Saurabh SINGH - Cedar Park TX, US
Aniruddha SATOSKAR - Austin TX, US

Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh

International Classification:

H03M 1/12
G06F 13/42
G06F 13/40

Abstract:

In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths and a controller. The plurality of processing paths may include a static processing path configured to generate a first digital signal based on an analog input signal and a dynamic processing path configured to generate a second digital signal based on the analog input signal, wherein a parameter of the dynamic processing path is determined based on a characteristic of the analog input signal. The controller may be configured to select the first digital signal as a digital output signal of the processing system when a change is occurring to the characteristic and select the second digital signal as the digital output signal in the absence of change occurring to the characteristic.