Scott O Frake

US Patent:

6366117, Apr 2, 2002

Filed:

Nov 28, 2000

Appl. No.:

09/724973

Inventors:

Raymond C. Pang - San Jose CA
Jennifer Wong - Fremont CA
Scott O. Frake - Cupertino CA
Jane W. Sowards - Fremont CA
Venu M. Kondapalli - Sunnyvale CA
F. Erich Goetting - Cupertino CA
Stephen M. Trimberger - San Jose CA
Kameswara K. Rao - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04L 900

US Classification:

326 38, 380 44, 713189, 326 40

Abstract:

It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.

US Patent:

6441641, Aug 27, 2002

Filed:

Nov 28, 2000

Appl. No.:

09/724735

Inventors:

Raymond C. Pang - San Jose CA
Venu M. Kondapalli - Sunnyvale CA
Jane W. Sowards - Fremont CA
Scott O. Frake - Cupertino CA
Jennifer Wong - Fremont CA
F. Erich Goetting - Cupertino CA
Peter H. Alfke - Los Altos Hills CA
Schuyler E. Shimanek - Albuquerque NM

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326 37, 326 46

Abstract:

A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.

US Patent:

6448809, Sep 10, 2002

Filed:

Aug 7, 2001

Appl. No.:

09/924356

Inventors:

F. Erich Goetting - Cupertino CA
Scott O. Frake - Cupertino CA
Venu M. Kondapalli - Sunnyvale CA
Steven P. Young - Boulder CO

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 738

US Classification:

326 44, 326 37, 326 47

Abstract:

The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

US Patent:

6526466, Feb 25, 2003

Filed:

Nov 12, 1999

Appl. No.:

09/438220

Inventors:

Scott O. Frake - Cupertino CA
James L. McManus - Campbell CA
David P. Schultz - San Jose CA
Wilson K. Yee - Pleasanton CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 1300

US Classification:

710302, 327530

Abstract:

An apparatus and method for enabling hot swapping of programmable logic devices (PLDs) and boards containing PLDs is provided. If the hot swap capability is desired, a hot swap terminal on the PLD is set to facilitate a floating state on the input/output pad of the PLD. Further, the input buffer and the output buffer of the PLD are disabled. In one embodiment, a predetermined voltage is provided on the output terminal of the input buffer. In this configuration, the hot swap circuit eliminates any leakage current, ensures no static current occurs, and provides appropriate signals to the internal circuits of the PLD.

US Patent:

6559715, May 6, 2003

Filed:

Jul 18, 2000

Appl. No.:

09/618204

Inventors:

Scott O. Frake - Cupertino CA
Jason R. Bergendahl - Campbell CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 500

US Classification:

327558, 327552

Abstract:

A low pass filter (LPF) is provided that smoothes and significantly slows any change in its input voltage. The capacitance of the LPF is provided by an NMOS transistor having its source and drain tied to ground. The resistance of the LPF is provided by a plurality of series-connected PMOS transistors. The gates of the PMOS transistors are coupled to ground and therefore these transistors are conducting. The PMOS transistors are fabricated in a floating well. Therefore, the LPF eliminates any capacitive coupling between a voltage supply and the well. Thus, any variation in the supply voltage fails to affect adversely the functioning of the PMOS transistors. Thus, the LPF of the present invention can advantageously smooth and significantly slow any change in its input voltage. In one embodiment, the input voltage is a reference voltage. In this manner, a voltage regulator, which receives the filtered reference voltage from the LPF, in turn provides a significantly more constant regulated voltage to the internal circuits of the IC.

US Patent:

62046918, Mar 20, 2001

Filed:

May 11, 2000

Appl. No.:

9/569745

Inventors:

F. Erich Goetting - Cupertino CA
Scott O. Frake - Cupertino CA
Venu M. Kondapalli - San Jose CA
Steven P. Young - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19094
H03K 19177

US Classification:

326 44

Abstract:

The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

US Patent:

62046950, Mar 20, 2001

Filed:

Jun 18, 1999

Appl. No.:

9/336357

Inventors:

Peter H. Alfke - Los Altos Hills CA
Alvin Y. Ching - San Jose CA
Scott O. Frake - Cupertino CA
Jennifer Wong - Fremont CA
Steven P. Young - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03H 19096

US Classification:

326 93

Abstract:

A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

US Patent:

49595652, Sep 25, 1990

Filed:

Feb 10, 1989

Appl. No.:

7/309253

Inventors:

Mark W. Knecht - Campbell CA
Scott O. Frake - Santa Clara CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 313
H03K 513
H03K 1728
H03K 17687

US Classification:

307542

Abstract:

A novel output buffer is described which includes a plurality of pull up transistors connected in parallel and/or a plurality of pull down transistors connected in parallel. A desired amount of resistance is included in the path connecting the gates of the pull up transistors, and in the path connecting the gates of the pull down transistors, thereby providing a distributed RC network causing pull up and pull down transistors to turn on in sequence. This is designed to keep the rate of change of the pull up and pull down current constant, thus reducing ground and Vcc bounce. In another embodiment, a single pull up transistor and/or a single pull down transistor is used. The single transistors have a relatively high gate resistance such that along the channel width of the transistor, the gate capacitance and the gate resistance operates as a distributed RC network. In this manner, portions of the channel begin conducting sequentially, as is the case where a plurality of pull up and pull down transistors are used.