Scott K Graham

US Patent:

20230042055, Feb 9, 2023

Filed:

Oct 20, 2022

Appl. No.:

17/969877

Inventors:

- Wright-Patterson AFB OH, US
Patrick Reber - Dayton OH, US
Patrick J. Sweeney - Beavercreek OH, US
Scott Graham - Beavercreek OH, US

International Classification:

G06F 21/57
G06F 9/4401
G06F 21/76
H04L 9/08
G06F 21/64

Abstract:

An active attestation apparatus verifies at runtime the integrity of untrusted machine code of an embedded system residing in a memory device while it is being run/used with while slowing the processing time less than other methods. The apparatus uses an integrated circuit chip containing a microcontroller and a reprogrammable logic device, such as a field programmable gate array (FPGA), to implement software attestation at runtime and in less time than is typically possible with comparable attestation approaches, while not requiring any halt of the processor in the microcontroller. The reprogrammable logic device includes functionality to load an encrypted version of its configuration and operating code, perform a checksum computation, and communicate with a verifier. The checksum algorithm is preferably time optimized to execute computations in the reprogrammable logic device in the minimum possible time.

US Patent:

20210294897, Sep 23, 2021

Filed:

Jun 8, 2021

Appl. No.:

17/341575

Inventors:

- Wright-Patterson AFB OH, US
Patrick Reber - Dayton OH, US
Patrick J. Sweeney - Beavercreek OH, US
Scott Graham - Beavercreek OH, US

International Classification:

G06F 21/56
G06F 21/60

Abstract:

An active attestation apparatus verifies at runtime the integrity of untrusted machine code of an embedded system residing in a memory device while it is being run/used with while slowing the processing time less than other methods. The apparatus uses an integrated circuit chip containing a microcontroller and a reprogrammable logic device, such as a field programmable gate array (FPGA), to implement software attestation at runtime and in less time than is typically possible with comparable attestation approaches, while not requiring any halt of the processor in the microcontroller. The reprogrammable logic device includes functionality to load an encrypted version of its configuration and operating code, perform a checksum computation, and communicate with a verifier. The checksum algorithm is preferably time optimized to execute computations in the reprogrammable logic device in the minimum possible time.