Scott A Kimura from 2178 Paseo Del Oro, San Jose, CA 95124, age 58, Phone: (408)3773519

Resumes

Engineer

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Location:

2178 Paseo Del Oro, San Jose, CA 95124

Industry:

Computer Hardware

Work:

Nvidia
Engineer

Skills:

Asic
Verilog
Soc
Rtl Design
Computer Architecture
Systemverilog
Debugging
Embedded Systems
Static Timing Analysis
Vlsi
Timing Closure
Logic Synthesis
Processors
Physical Design
Primetime
Perl
Semiconductors

Interests:

Exercise
Sweepstakes
Home Improvement
Reading
Gourmet Cooking
Sports
Home Decoration
Cooking
Electronics
Outdoors
Crafts
Music
Movies
Kids
Automobiles
Travel
Boating
Investing
Traveling
International Traavel

Languages:

English

Scott Kimura

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Us Patents

Sliced Crossbar Architecture With No Inter-Slice Communication
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US Patent:

6961803, Nov 1, 2005
Filed:

Aug 8, 2001
Appl. No.:

09/925156
Inventors:

Stephen Clark Purcell - Mountain View CA, US
Scott Kimura - San Jose CA, US
Assignee:

Pasternak Solutions LLC - Los Altos CA
International Classification:

G06F013/00
US Classification:

710317, 710242
Abstract:

A method and apparatus includes identifying a first portion of a first message in a first slice of a switch, the first message associated with a first priority, the first portion of the first message including a first routing portion specifying a network resource; identifying a second portion of the first message in a second slice of the switch, the second portion of the first message including the first routing portion; identifying a first portion of a second message in the first slice, the second message associated with a second priority, the first portion of the second message including a second routing portion specifying the network resource; identifying a second portion of the second message in the second slice, the second portion of the second message including the second routing portion; selecting, independently in each slice, the same one of the first and second messages based on the first and second priorities; sending the first portion of the selected message from the first slice to the network resource specified by the one of the first and second routing portions corresponding to the selected message; and sending the second portion of the selected message from the second slice to the network resource specified by the one of the first and second routing portions corresponding to the selected message.

Sliced Crossbar Architecture With Inter-Slice Communication
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US Patent:

6970454, Nov 29, 2005
Filed:

Aug 9, 2001
Appl. No.:

09/927306
Inventors:

Stephen Clark Purcell - Mountain View CA, US
Scott Kimura - San Jose CA, US
Assignee:

Pasternak Solutions LLC - Los Altos CA
International Classification:

H04L012/56
H04Q011/04
US Classification:

370355, 370392, 37039542, 370412, 370428, 709226, 709238
Abstract:

A method and apparatus includes identifying an address portion of a first message in an address slice of a switch, the first message associated with a first priority, the address portion of the first message including a first routing portion specifying a network resource; identifying an address portion of a second message in the address slice, the second message associated with a second priority, the address portion of the second message including a second routing portion specifying the same network resource; identifying a non-address portion of the first message in a non-address slice of the switch; identifying a non-address portion of the second message in the non-address slice, wherein neither of the non-address portions includes a routing portion specifying the network resource; selecting, independently in each slice, the same one of the first and second messages based on the first and second priorities; transferring the address portion of the selected message to the network resource specified by the routing portion of the address portion of the selected message; sending the routing portion of the address portion of the selected message from the address slice to the non-address slice; transferring the non-address portion of the selected message to the network resource specified by the routing portion of the address portion of the selected message.

Method And Apparatus For Generating Random Numbers For Use In A Field Programmable Gate Array
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US Patent:

7072924, Jul 4, 2006
Filed:

Aug 25, 2004
Appl. No.:

10/711115
Inventors:

Stephen Clark Purcell - Mountain View CA, US
Scott Kimura - San Jose CA, US
Rajeshwaran Selvanesan - Milpitas CA, US
International Classification:

G06F 1/02
US Classification:

708256, 708253
Abstract:

A method and apparatus for generating random number outputs utilized in generating a noise function at a given location in space. The method consists of partitioning selected portions of the random number generation process to achieve outputs in parallel. The relevant parallel outputs are weighted by effect and then summed together to give the amplitude of the noise function at the given location.

Method And Apparatus For Generating Random Numbers For Use In A Field Programmable Gate Array
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US Patent:

7072927, Jul 4, 2006
Filed:

Aug 8, 2001
Appl. No.:

09/925155
Inventors:

Stephen Clark Purcell - Mountain View CA, US
Scott Kimura - San Jose CA, US
Rajeshwaran Selvanesan - Milpitas CA, US
International Classification:

G06F 17/10
G06F 1/02
US Classification:

708300, 708256
Abstract:

A method and apparatus for generating random number outputs utilized in generating a noise function at a given location in space. The method consists of partitioning selected portions of the random number generation process to achieve outputs in parallel. The relevant parallel outputs are weighted by effect and then summed together to give the amplitude of the noise function at the given location.

Memory Bus Arbitration Using Memory Bank Readiness
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US Patent:

7107386, Sep 12, 2006
Filed:

Jan 15, 2004
Appl. No.:

10/759376
Inventors:

Stephen Clark Purcell - Mountain View CA, US
Scott Kimura - San Jose CA, US
Assignee:

Pasternak Solutions, LLC - Los Altos CA
International Classification:

G06F 13/00
US Classification:

711 5, 711151, 711158, 710 39, 710240, 710244
Abstract:

A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.

One-Way Transaction Tagging In A Switch Crossbar
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US Patent:

7139836, Nov 21, 2006
Filed:

Aug 8, 2001
Appl. No.:

09/925160
Inventors:

Stephen Clark Purcell - Mountain View CA, US
Scott Kimura - San Jose CA, US
International Classification:

G06F 15/173
US Classification:

709238, 709213, 709214, 709215, 370355, 370392, 370428
Abstract:

A method and computer program product includes, at a sender, identifying a forward item including a transmit portion and a retain portion, generating a tag, associating the tag with the retain portion, sending the transmit portion, but not the tag, to a target; at the target, receiving the transmit portion, identifying a return portion corresponding to the transmit portion, independently generating the tag, associating the tag with the return portion, sending the return portion and the tag to the sender; and at the sender, receiving the return portion and the tag, identifying the retain portion using the tag, and associating the return portion with the retain portion to create a reverse item.

Method And Apparatus For Accumulating Floating Point Values
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US Patent:

7212959, May 1, 2007
Filed:

Aug 8, 2001
Appl. No.:

09/925161
Inventors:

Stephen Clark Purcell - Mountain View CA, US
Scott Kimura - San Jose CA, US
Mark L. Wood Patrick - Sunnyvale CA, US
International Classification:

G06F 7/62
US Classification:

703 13, 703 14, 703 15, 708524, 708495, 708620, 708629, 712220, 712221, 712222
Abstract:

A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for directing initial inputs and intermediate result values.

Sliced Crossbar Architecture With No Inter-Slice Communication
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US Patent:

7249214, Jul 24, 2007
Filed:

Sep 1, 2005
Appl. No.:

11/218963
Inventors:

Stephen Clark Purcell - Mountain View CA, US
Scott Kimura - San Jose CA, US
International Classification:

G06F 13/00
US Classification:

710317, 709238
Abstract:

A method and apparatus includes identifying a first portion of a first message in a first slice of a switch, the first message associated with a first priority, the first portion of the first message including a first routing portion specifying a network resource; identifying a second portion of the first message in a second slice of the switch, the second portion of the first message including the first routing portion; identifying a first portion of a second message in the first slice, the second message associated with a second priority, the first portion of the second message including a second routing portion specifying the network resource; identifying a second portion of the second message in the second slice, the second portion of the second message including the second routing portion; selecting, independently in each slice, the same one of the first and second messages based on the first and second priorities; sending the first portion of the selected message from the first slice to the network resource specified by the one of the first and second routing portions corresponding to the selected message; and sending the second portion of the selected message from the second slice to the network resource specified by the one of the first and second routing portions corresponding to the selected message.