Scott D Lindsey

US Patent:

20030183416, Oct 2, 2003

Filed:

Mar 29, 2002

Appl. No.:

10/113026

Inventors:

Jerry White - Glendale AZ, US
Scott Lindsey - Brentwood CA, US
Drew Delaney - Gilbert AZ, US

International Classification:

H05K001/18
H05K003/30

US Classification:

174/257000, 174/260000, 029/842000, 029/840000

Abstract:

A method of electrically coupling a first substrate () and a second substrate () includes forming a conductive bump () on the first substrate () by electroless plating a metal and nonconductive particles () together. The first substrate () and the second substrate () are bonded with a nonconductive polymer () so that the conductive bump () and a conductive pad () of the second substrate ) are electrically coupled.

US Patent:

57739862, Jun 30, 1998

Filed:

Apr 3, 1995

Appl. No.:

8/416121

Inventors:

Patrick F. Thompson - Chandler AZ
William M. Williams - Gilbert AZ
Scott E. Lindsey - Mesa AZ
Barbara Vasquez - Austin TX

Assignee:

Motorola, Inc - Schaumburg IL

International Classification:

G01R 1073

US Classification:

324754

Abstract:

A semiconductor wafer contact system includes a sealed bladder (32) containing incompressible material. The sealed bladder (32) presses against a flexible circuit layer (28) including an array of electrical contacts (30). The bladder (32) forces the array of electrical contacts (30) against a corresponding array of device electrical contacts (12) on die (11) of a semiconductor wafer (10). The bladder (32) adapts in shape to compensate for die level and wafer level irregularities in contact height and non-parallelism. Additionally, bladder (32) ensures a constant force between membrane contacts (30) and die contacts (12), across the entire wafer (10).

US Patent:

56296304, May 13, 1997

Filed:

Feb 27, 1995

Appl. No.:

8/395127

Inventors:

Patrick F. Thompson - Chandler AZ
William M. Williams - Gilbert AZ
Scott E. Lindsey - Mesa AZ
Barbara Vasquez - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G01R 106

US Classification:

324754

Abstract:

A semiconductor wafer contact system includes a base substrate (13) which has an array of raised supports (18). The array of raised supports (18) are distributed in a pattern corresponding to the pattern of electrical contacts (12) on the semiconductor wafer (10), to be contacted. In between the base substrate (13) and the wafer to be contacted (10) is a flexible circuit layer (14) including an array of electrical contacts (15) having the same pattern as the contacts (12) of the wafer and the raised supports (18). The raised supports (18) provide focused and localized force, pressing the membrane test contacts (15) against the wafer electrical contacts (12).

US Patent:

63104032, Oct 30, 2001

Filed:

Aug 31, 2000

Appl. No.:

9/652620

Inventors:

Chunsheng Zhang - Chandler AZ
Jong-Kai Lin - Chandler AZ
Scott E. Lindsey - Mesa AZ
Yifan Guo - Gilbert AZ
Li Li - Gilbert AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2348
H01L 2352
H01L 2940

US Classification:

257786

Abstract:

A method of manufacturing components includes providing a substrate (110, 531, 631, 700) having a first coefficient of thermal expansion (CTE), having a first surface (111), and supporting a first plurality of interconnects located over the first surface in a first predetermined pattern. The method also includes providing another substrate (190) having a second CTE, having a second surface (195), and supporting a second plurality of interconnects located over the second surface in a second predetermined pattern. The method further includes assembling together the two substrates at a first temperature outside of a temperature range of approximately 25 to 30. degree. C.