Scott F Weber

US Patent:

8650514, Feb 11, 2014

Filed:

Mar 21, 2012

Appl. No.:

13/426592

Inventors:

Scott J. Weber - Piedmont CA, US
Christopher D. Ebeling - San Jose CA, US
Andrew Caldwell - Santa Clara CA, US
Steven Teig - Menlo Park CA, US
Timothy J. Callahan - Mantorville MN, US
Hung Q. Nguyen - San Jose CA, US
Shangzhi Sun - San Jose CA, US
Shilpa V. Yeole - Milpitas CA, US

Assignee:

Tabula, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716101

Abstract:

A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

US Patent:

20130097575, Apr 18, 2013

Filed:

Apr 6, 2011

Appl. No.:

13/806767

Inventors:

Scott J. Weber - Piedmont CA, US
Christopher D. Ebeling - San Jose CA, US
Andrew Caldwell - Santa Clara CA, US
Steven Teig - Menlo Park CA, US
Timothy J. Callahan - Mantorville MN, US
Hung Q. Nguyen - San Jose CA, US
Shangzhi Sun - San Jose CA, US
Shilpa V. Yeole - Milpitas CA, US

Assignee:

TABULA, INC. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716129, 716134

Abstract:

A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

US Patent:

20220294454, Sep 15, 2022

Filed:

Mar 31, 2022

Appl. No.:

17/710628

Inventors:

- Santa Clara CA, US
Scott J. Weber - Piedmont CA, US
Ravi Prakash Gutala - San Jose CA, US
Aravind Raghavendra Dasu - Milpitas CA, US

International Classification:

H03K 19/17758
H03K 19/1776
H03K 19/17796
H03K 19/17772
H03K 19/17768

Abstract:

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.

US Patent:

20220221986, Jul 14, 2022

Filed:

Apr 1, 2022

Appl. No.:

17/711840

Inventors:

Scott Jeremy Weber - Piedmont CA, US
Ashish Gupta - San Jose CA, US
Navid Azizi - Toronto, CA
Ilya K. Ganusov - San Jose CA, US
Kalen Brunham - Toronto, CA
Przemek Guzy - Oakville, CA
Rajiv Kumar - Pulau, MY
Thuyet Ngo - Bayan Lepas, MY
Mark Honman - Holmer Green, GB

International Classification:

G06F 3/06

Abstract:

An integrated circuit device includes a programmable fabric that has a plurality of memory blocks. The integrated circuit device also includes a network-on-chip (NOC) located on a shoreline of the programmable fabric and at least one micro NOC formed with hardened resources in the programmable fabric. The at least one micro NOC is communicatively coupled to the NOC and to at least one memory block of the plurality of memory blocks. Additionally, the at least one micro NOC is configurable to route data between the NOC and the at least one memory block.

US Patent:

20230056118, Feb 23, 2023

Filed:

Aug 22, 2022

Appl. No.:

17/893004

Inventors:

- Santa Clara CA, US
Scott J. Weber - Piedmont CA, US
James Ball - San Jose CA, US
Ravi Prakash Gutala - San Jose CA, US
Aravind Raghavendra Dasu - Milpitas CA, US

International Classification:

H03K 19/1776
G11C 7/10
H01L 25/065
G11C 5/02

Abstract:

An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.

US Patent:

20210117268, Apr 22, 2021

Filed:

Dec 23, 2020

Appl. No.:

17/132221

Inventors:

- Santa Clara CA, US
Scott Weber - Piedmont CA, US
Alpa Trivedi - Portland OR, US
Steffen Schulz - Darmstadt, DE
Sriram Vangal - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/07
G06N 20/00
G06F 21/71

Abstract:

An apparatus to facilitate runtime fault detection, fault location, and circuit recovery in an accelerator device is disclosed. In one implementation, the accelerator device comprises a sensor network comprising a plurality of sensors; a secure device manager (SDM); and a sensor aggregator communicably coupled to the sensor network and the SDM. In one implementation, the sensor aggregator can receive sensor data from the sensor network; analyze the sensor data to detect a fault condition; determine a spatial location of the fault condition based on the sensor data; and generate an event for the SDM to cause the SDM to mitigate the fault condition.

US Patent:

20210110069, Apr 15, 2021

Filed:

Dec 21, 2020

Appl. No.:

17/129250

Inventors:

- Santa Clara CA, US
Scott Weber - Piedmont CA, US
Steffen Schulz - Darmstadt, DE
Patrick Koeberl - Alsbach-Haenlein, DE

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 21/76
G06F 21/57
G06F 21/53
G06F 21/30

Abstract:

An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to receive an incoming partial reconfiguration (PR) bitstream corresponding to a new PR persona to configure a region of the apparatus; perform, as part of a PR configuration sequence for the new PR persona, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation, the second clear operation performed using a persona-dependent mask corresponding to the new PR persona.

US Patent:

20210058085, Feb 25, 2021

Filed:

Nov 10, 2020

Appl. No.:

17/094612

Inventors:

- Santa Clara CA, US
Scott J. Weber - Piedmont CA, US
James Ball - San Jose CA, US
Ravi Prakash Gutala - San Jose CA, US
Aravind Raghavendra Dasu - Milpitas CA, US

International Classification:

H03K 19/1776
G11C 7/10
H01L 25/065
G11C 5/02

Abstract:

An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.