Scott Wu

US Patent:

8338934, Dec 25, 2012

Filed:

Mar 16, 2011

Appl. No.:

13/049550

Inventors:

Albert Wu - Palo Alto CA, US
Scott Wu - San Jose CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H01L 23/22

US Classification:

257687

Abstract:

Embodiments of the present disclosure provide a substrate having (i) a first laminate layer, (ii) a second laminate layer, and (iii) a core material that is disposed between the first laminate layer and the second laminate layer; and a die attached to the first laminate layer, the die having an interposer bonded to a surface of an active side of the die, the surface comprising (i) a dielectric material and (ii) a bond pad to route electrical signals of the die, the interposer having a via formed therein, the via being electrically coupled to the bond pad to further route the electrical signals of the die, wherein the die and the interposer are embedded in the core material of the substrate. Other embodiments may be described and/or claimed.

US Patent:

20110121444, May 26, 2011

Filed:

Nov 9, 2010

Appl. No.:

12/942918

Inventors:

Albert Wu - Palo Alto CA, US
Scott Wu - San Jose CA, US

International Classification:

H01L 21/56
H01L 23/498

US Classification:

257693, 438124, 257E21502, 257E23069

Abstract:

Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed.

US Patent:

20110186960, Aug 4, 2011

Filed:

Jan 14, 2011

Appl. No.:

13/007059

Inventors:

Albert Wu - Palo Alto CA, US
Roawen Chen - Monte Sereno CA, US
Chung Chyung Han - San Jose CA, US
Chien-Chuan Wei - Los Gatos CA, US
Runzi Chang - San Jose CA, US
Scott Wu - San Jose CA, US
Chuan-Cheng Cheng - Premont CA, US

International Classification:

H01L 27/04
H01L 23/488
H01L 21/60
H01L 21/98

US Classification:

257508, 257738, 438108, 257E21506, 257E21705, 257E2701, 257E23023

Abstract:

Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.

US Patent:

20110186992, Aug 4, 2011

Filed:

Jan 28, 2011

Appl. No.:

13/015988

Inventors:

Albert Wu - Palo Alto CA, US
Roawen Chen - Monte Sereno CA, US
Chung Chyung Han - San Jose CA, US
Chien-Chuan Wei - Los Gatos CA, US
Runzi Chang - San Jose CA, US
Scott Wu - San Jose CA, US
Chuan-Cheng Cheng - Fremont CA, US

International Classification:

H01L 23/48
H01L 21/56

US Classification:

257737, 438108, 257774, 257E2301, 257E23011, 257E21502

Abstract:

Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

US Patent:

20110186998, Aug 4, 2011

Filed:

Jan 24, 2011

Appl. No.:

13/012644

Inventors:

Albert Wu - Palo Alto CA, US
Roawen Chen - Monte Sereno CA, US
Chung Chyung Han - San Jose CA, US
Chien-Chuan Wei - Los Gatos CA, US
Runzi Chang - San Jose CA, US
Scott Wu - San Jose CA, US
Chuan-Cheng Cheng - Fremont CA, US

International Classification:

H01L 23/48
H01L 21/50

US Classification:

257738, 438108, 257E23011, 257E21499, 257774, 257E23023

Abstract:

Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.

US Patent:

20150228569, Aug 13, 2015

Filed:

Feb 3, 2015

Appl. No.:

14/613218

Inventors:

- St. Michael, BB
Albert Wu - Palo Alto CA, US
Scott Wu - San Jose CA, US

International Classification:

H01L 23/498
H05K 1/18
H05K 1/11
H01L 21/48
H05K 1/03

Abstract:

Some of the embodiments of the present disclosure provide a semiconductor package interposer comprising a substrate having a first surface and a second surface, a plurality of vias extending between the first surface and the second surface of the substrate, the plurality of vias electrically connecting electrical connectors or circuitry on the first surface of the substrate to electrical connectors or circuitry on the second surface of the substrate, and metal plugs at least partially filling the plurality of vias. At least one of (i) the first surface or (ii) the second surface of the substrate includes depressions at distal ends of the metal plugs.

US Patent:

20140106508, Apr 17, 2014

Filed:

Dec 24, 2013

Appl. No.:

14/140149

Inventors:

- St. Michael, BB
Albert Wu - Palo Alto CA, US
Scott Wu - San Jose CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H01L 25/00

US Classification:

438109

Abstract:

Embodiments of the present disclosure provide a method that comprises providing a first die having a surface comprising a bond pad to route electrical signals of the first die and attaching the first die to a layer of a substrate. The method further comprises forming one or more additional layers of the substrate to embed the first die in the substrate and coupling a second die to the one or more additional layers, the second die having a surface comprising a bond pad to route electrical signals of the second die. The second die is coupled to the one or more additional layers such that electrical signals are routed between the first die and the second die.