Shahriar Seyedhosseini
age ~53
from Des Moines, IA
- Also known as:
-
- Shahriar H Seyedhossein
- Shahrian Seyed Hosseini
Shahriar Seyedhosseini Phones & Addresses
- Des Moines, IA
- 709 Modern Ice Dr, San Jose, CA 95112
- Chadds Ford, PA
- Webster City, IA
- 5 Dee Cir, Downingtown, PA 19335 • (610)4587371
- Newtown, PA
- Chester, PA
Work
-
Company:AquantiaOct 2012
-
Address:Milpitas, CA
-
Position:Senior technical member of staff
Education
-
School / High School:Villanova University2003 to 2005
Skills
Verilog • Fpga • Debugging • Systemverilog • Asic • Pcie • Embedded Systems • Soc • Hardware Architecture • Perl • Integrated Circuit Design • System Verilog • Testing • Application Specific Integrated Circuits • C • Hardware • Hardware Verification • Xilinx • Functional Verification • Rtl Design • Ethernet • Embedded Software • C++ • Firmware • Computer Hardware • Low Power Systems • Computer Architecture • Logic Design • Open Verification Methodology • Vera • Objective C • Java • Android • Ios Development • Specman • Upf • Processors • Static Timing Analysis • Tcl • Vlsi • Eda • Modelsim • Semiconductors • Shell Scripting • Ic • Sva • Universal Verification Methodology • Artificial Intelligence • Process Optimization • Start Ups • Computer Science • Python • Recurrent Neural Networks • Tensorflow • Management • Convolutional Neural Networks • Deep Learning • Artificial Neural Networks • Compiler • Tpu • Resnet50 • Distributed Computations • Hands on Technical Leadership • Data Science • Cross Functional Team Leadership
Languages
English • Farsi
Interests
New Ventures • Science and Technology • Children • Education
Industries
Computer Hardware
Resumes
Deep Learning Hardware Engineering Manager
view sourceLocation:
2764 Bungalow Ct, San Jose, CA 95125
Industry:
Computer Hardware
Work:
Aquantia - Milpitas, CA since Oct 2012
Senior Technical Member of Staff
Chelsio Communications - Sunnyvale, ca Aug 2012 - Oct 2012
ASIC Verification Manager
Chelsio Communications May 2007 - Aug 2012
Senior Hardware Verification Engineer
Electrolux Major Appliances 2005 - 2006
Design Engineer
Unisys Sep 1999 - May 2005
Hardware Engineer
Senior Technical Member of Staff
Chelsio Communications - Sunnyvale, ca Aug 2012 - Oct 2012
ASIC Verification Manager
Chelsio Communications May 2007 - Aug 2012
Senior Hardware Verification Engineer
Electrolux Major Appliances 2005 - 2006
Design Engineer
Unisys Sep 1999 - May 2005
Hardware Engineer
Education:
Villanova University 2003 - 2005
Drexel University 1998 - 2002
Drexel University 1998 - 2002
Skills:
Verilog
Fpga
Debugging
Systemverilog
Asic
Pcie
Embedded Systems
Soc
Hardware Architecture
Perl
Integrated Circuit Design
System Verilog
Testing
Application Specific Integrated Circuits
C
Hardware
Hardware Verification
Xilinx
Functional Verification
Rtl Design
Ethernet
Embedded Software
C++
Firmware
Computer Hardware
Low Power Systems
Computer Architecture
Logic Design
Open Verification Methodology
Vera
Objective C
Java
Android
Ios Development
Specman
Upf
Processors
Static Timing Analysis
Tcl
Vlsi
Eda
Modelsim
Semiconductors
Shell Scripting
Ic
Sva
Universal Verification Methodology
Artificial Intelligence
Process Optimization
Start Ups
Computer Science
Python
Recurrent Neural Networks
Tensorflow
Management
Convolutional Neural Networks
Deep Learning
Artificial Neural Networks
Compiler
Tpu
Resnet50
Distributed Computations
Hands on Technical Leadership
Data Science
Cross Functional Team Leadership
Fpga
Debugging
Systemverilog
Asic
Pcie
Embedded Systems
Soc
Hardware Architecture
Perl
Integrated Circuit Design
System Verilog
Testing
Application Specific Integrated Circuits
C
Hardware
Hardware Verification
Xilinx
Functional Verification
Rtl Design
Ethernet
Embedded Software
C++
Firmware
Computer Hardware
Low Power Systems
Computer Architecture
Logic Design
Open Verification Methodology
Vera
Objective C
Java
Android
Ios Development
Specman
Upf
Processors
Static Timing Analysis
Tcl
Vlsi
Eda
Modelsim
Semiconductors
Shell Scripting
Ic
Sva
Universal Verification Methodology
Artificial Intelligence
Process Optimization
Start Ups
Computer Science
Python
Recurrent Neural Networks
Tensorflow
Management
Convolutional Neural Networks
Deep Learning
Artificial Neural Networks
Compiler
Tpu
Resnet50
Distributed Computations
Hands on Technical Leadership
Data Science
Cross Functional Team Leadership
Interests:
New Ventures
Science and Technology
Children
Education
Science and Technology
Children
Education
Languages:
English
Farsi
Farsi
Us Patents
-
Hardware-Implemented Lzw Data Decompression
view source -
US Patent:7071854, Jul 4, 2006
-
Filed:May 9, 2003
-
Appl. No.:10/435647
-
Inventors:Carlos Cardosa - Philadelphia PA, US
Shahriar Seyedhosseini - Chadds Ford PA, US
Anil Varghese - Philadelphia PA, US -
Assignee:Unisys Corporation - Blue Bell PA
-
International Classification:H03M 7/40
-
US Classification:341 67, 341 51, 341 87
-
Abstract:An apparatus for performing LZW data decompression in hardware is described. In one exemplary implementation, the apparatus includes processing modules configured to decompress compressed data using an LZW data decompression algorithm. Operations associated with decompressing the compressed data are segmented into stages. For each particular stage, one or more of the processing modules are assigned to perform operations appurtenant to that particular stage and collectively decompress the compressed data. Each processing module is implemented in hardware and configured to operate independently with respect to the operations appurtenant to that processing module.
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