Shashank C Deshmukh

US Patent:

6402974, Jun 11, 2002

Filed:

Jul 27, 1999

Appl. No.:

09/361683

Inventors:

Jitske Trevor - Sunnyvale CA
Shashank Deshmukh - Sunnyvale CA
Jeff Chinn - Foster City CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23F 700

US Classification:

216 67, 216 64, 216 70, 216 79, 156345, 438712, 438719, 438735

Abstract:

In accordance with the present invention, during a polysilicon etch back, a controlled amount of oxygen (O ) is added to the plasma generation feed gases, to reduce pitting of the etched back polysilicon surface. The plasma etchant is generated from a plasma source gas comprising: (i) at least one fluorine-containing gas, and (ii) oxygen. The invention may be practiced in any of a number of apparatus adapted to expose polysilicon to a plasma etchant. One preferred apparatus is a decoupled plasma source (DPSâ, Applied Materials, Santa Clara, Calif. ) etching system. Another preferred apparatus is a magnetically enhanced plasma (MXPâ, Applied Materials, Santa Clara, Calif. ) etching system. Preferably, the invention is practiced in an apparatus having a memory that stores instructions for carrying out the process of the invention, a processor adapted to communicate with the memory and to execute the instructions stored by the memory, an etch chamber adapted to expose the substrate to the etchant in accordance with instructions from the processor, and a port adapted to pass communications between the processor and the etch chamber.

US Patent:

6653237, Nov 25, 2003

Filed:

Jun 27, 2001

Appl. No.:

09/893859

Inventors:

Shashank Deshmukh - San Jose CA
David Mui - San Jose CA
Jeffrey D. Chinn - Foster City CA
Dragan V Podlesnik - Palo Alto CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438700, 438706, 438712, 438719

Abstract:

Processes for forming trenches within silicon substrates are described. According to an embodiment of the invention, a masked substrate is initially provided that comprises (a) a silicon substrate and (b) a patterned resist layer over the silicon substrate. The patterned resist layer has one or more apertures formed therein. Subsequently, a trench is formed in the substrate through the apertures in the resist layer by an inductive plasma-etching step, which is conducted using plasma source gases that comprise SF , at least one fluorocarbon gas, and N. If desired, Cl can also be provided in addition to the above source gases. The process of the present invention produces chamber deposits in low amounts, while providing high etching rates, high silicon:resist selectivities, and good trench sidewall profile control.

US Patent:

6921723, Jul 26, 2005

Filed:

Apr 23, 2002

Appl. No.:

10/128907

Inventors:

Yung-Hee Yvette Lee - San Jose CA, US
Shashank Deshmukh - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L021/302

US Classification:

438710, 438714, 438717, 438718, 438719, 438724, 438725

Abstract:

Conventional methods of semiconductor fabrication and processing typically utilize three gas (e. g. , HBr, Cland O) and four gas (e. g. , HBr, Cl, Oand CF) chemistries to perform gate etching in plasma process chambers. However, the silicon to resist selectivity achieved by these chemistries is limited to about 3:1. The present invention concerns a plasma source gas comprising SFand one or more fluorine-containing gases selected from CF, CF, CF, CHF, CHF, and CF(e. g. , SFand CF), allowing the use of a two gas etch chemistry that provides enhanced silicon to photoresist selectivity in gate etching processes.

US Patent:

6924088, Aug 2, 2005

Filed:

Jun 18, 2003

Appl. No.:

10/464479

Inventors:

David S. L. Mui - Fremont CA, US
Wei Liu - San Jose CA, US
Shashank C. Deshmukh - San Jose CA, US
Hiroki Sasano - Sunnyvale CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G01B011/02
H01L021/66

US Classification:

430313, 430 30, 15634524, 356635, 356636, 118696, 438 7, 438 16

Abstract:

A method and apparatus for processing a semiconductor wafer is provided for reducing CD microloading variation. OCD metrology is used to inspect a wafer to determine pre-etch CD microloading, by measuring the CD of dense and isolated photoresist lines. Other parameters can also be measured or otherwise determined, such as sidewall profile, photoresist layer thickness, underlying layer thickness, photoresist pattern density, open area, etc. The inspection results are fed forward to the etcher to determine process parameters, such as resist trim time and/or etch conditions, thereby achieving the desired post-etch CD microloading. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.

US Patent:

7122125, Oct 17, 2006

Filed:

Nov 4, 2002

Appl. No.:

10/288344

Inventors:

Shashank C. Deshmukh - San Jose CA, US
Thorsten B. Lill - Santa Clara CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B44C 1/22

US Classification:

216 63, 216 64, 216 71, 216 77

Abstract:

An integrated etch process, for example as used for etching an anti-reflection layer and an underlying aluminum layer, in which the chamber wall polymerization is controlled by coating polymer onto the sidewall by a plasma deposition process prior to inserting the wafer into the chamber, etching the structure, and after removing the wafer from the chamber, plasma cleaning the polymer from the chamber wall. The process is process is particularly useful when the etching is performed in a multi-step process and the polymer is used for passivating the etched structure, for example, a sidewall in an etched structure and in which the first etching step deposits polymer and the second etching step removes polymer. The controlled polymerization eliminates interactions of the etching with the chamber wall material, produces repeatable results between wafers, and eliminates in the etching plasma instabilities associated with changing wall conditions.

US Patent:

7368392, May 6, 2008

Filed:

Apr 23, 2004

Appl. No.:

10/831406

Inventors:

Jinhan Choi - San Jose CA, US
Shashank Deshmukh - San Jose CA, US
Sang Yi - Sunnyvale CA, US
Kyeong-Tae Lee - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/302

US Classification:

438706, 438689, 438671, 438712, 438720, 438942, 257750, 257758

Abstract:

A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ultra-thin (about 10 to 20 Angstroms) silicon dioxide gate dielectric, and a polysilicon upper contact. In a further embodiment, the gate electrode is selectively notched to a pre-determined width.

US Patent:

7504338, Mar 17, 2009

Filed:

Aug 9, 2006

Appl. No.:

11/502163

Inventors:

Yan Du - Sunnyvale CA, US
Meihua Shen - Fremont CA, US
Shashank Deshmukh - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/311
H01L 21/302

US Classification:

438694, 438710, 438723, 438724

Abstract:

Disclosed herein is a method of pattern etching a layer of a silicon-containing dielectric material. The method employs a plasma source gas including CFto CHF, where the volumetric ratio of CFto CHFis within the range of about 2:3 to about 3:1; more typically, about 1:1 to about 2:1. Etching is performed at a process chamber pressure within the range of about 4 mTorr to about 60 mTorr. The method provides a selectivity for etching a silicon-containing dielectric layer relative to photoresist of 1. 5:1 or better. The method also provides an etch profile sidewall angle ranging from 88 to 92 between said etched silicon-containing dielectric layer and an underlying horizontal layer. in the semiconductor structure. The method provides a smooth sidewall when used in combination with certain photoresists which are sensitive to 193 nm radiation.

US Patent:

7718538, May 18, 2010

Filed:

Feb 21, 2007

Appl. No.:

11/677472

Inventors:

Tae Won Kim - San Jose CA, US
Kyeong-Tae Lee - San Jose CA, US
Alexander Paterson - San Jose CA, US
Valentin N. Todorov - Palo Alto CA, US
Shashank C. Deshmukh - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/302

US Classification:

438714, 438706, 438710, 216 58

Abstract:

A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.