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Shaul A Teplinsky

age ~54

from Orinda, CA

Shaul Teplinsky Phones & Addresses

  • Orinda, CA
  • 325 Berry St #720, San Francisco, CA 94158
  • 1732 Parkview Green Cir, San Jose, CA 95131
  • Sunnyvale, CA
  • Milpitas, CA
  • Sanger, CA
  • Evart, MI

Skills

Semiconductors • Design of Experiments • Jmp • R&D • Data Analysis • Spc • Process Integration • Physics • Semiconductor Industry • Mems • Process Simulation • Statistics • Data Mining • Silicon • Patents • Solar Energy • Device Physics • Sql • Optimization • Intellectual Property • Reliability Engineering • Doe • Information Theory • Jsl • Vba • Solar • Semiconductor Manufacturing • Python • Tableau • Regular Expressions • Engineering Management • Thin Films • Research and Development • Statistical Process Control

Languages

English • Russian • Hebrew

Industries

Information Technology And Services

Resumes

Shaul Teplinsky Photo 1

Shaul A Teplinsky

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Location:
17 Wild Rye Way, Orinda, CA 94563
Industry:
Information Technology And Services
Skills:
Semiconductors
Design of Experiments
Jmp
R&D
Data Analysis
Spc
Process Integration
Physics
Semiconductor Industry
Mems
Process Simulation
Statistics
Data Mining
Silicon
Patents
Solar Energy
Device Physics
Sql
Optimization
Intellectual Property
Reliability Engineering
Doe
Information Theory
Jsl
Vba
Solar
Semiconductor Manufacturing
Python
Tableau
Regular Expressions
Engineering Management
Thin Films
Research and Development
Statistical Process Control
Languages:
English
Russian
Hebrew

Us Patents

  • Methods And Systems For Detecting Defects On An Electronic Assembly

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  • US Patent:
    20210041501, Feb 11, 2021
  • Filed:
    Mar 20, 2019
  • Appl. No.:
    16/981951
  • Inventors:
    - Holon, IL
    Gal PELED - Ezer, IL
    Dan SEBBAN - Rishon LeZion, IL
    Shaul TEPLINSKY - San Francisco CA, US
  • International Classification:
    G01R 31/3185
    H01L 21/66
    G01R 31/317
  • Abstract:
    A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight other nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.
  • Methods And Systems For Testing A Tester

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  • US Patent:
    20200116789, Apr 16, 2020
  • Filed:
    Oct 16, 2018
  • Appl. No.:
    16/161849
  • Inventors:
    - Holon, IL
    Dan GLOTTER - Tel-Aviv, IL
    Shaul TEPLINSKY - San Francisco CA, US
  • International Classification:
    G01R 31/319
    G01R 31/3193
    G01R 31/317
  • Abstract:
    A method of testing a tester, comprising testing electronic units using a plurality of sites in order to obtain first bin assignment, instructing the tester to perform a tester quality test if conditions Cand Care met, the tester quality test comprising performing a second plurality of tests on an electronic unit using a first site, thereby obtaining second bin assignment for the electronic unit, the second bin assignment being representative of passing or failing of the electronic unit of the second plurality of tests with respect to at least one second test criteria, wherein Cis met if passing first bin assignment has been obtained for said electronic unit connected to the tester using the first site, and wherein Cis met if data representative of passing first bin assignment obtained for electronic units which have been tested on the first site, meets a quality criteria.
  • Dynamic Process For Adaptive Tests

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  • US Patent:
    20170160342, Jun 8, 2017
  • Filed:
    Dec 3, 2015
  • Appl. No.:
    14/958462
  • Inventors:
    - Holon, IL
    Arie PELTZ - Nes Ziona, IL
    Shaul TEPLINSKY - San Francisco CA, US
  • International Classification:
    G01R 31/317
    G01R 31/3177
  • Abstract:
    A method for modifying the execution sequence of tests for testing an object on a test system. The tests include a group of tests that is a candidate for replacement. The method includes: while executing the tests according to the execution sequence and before executing the group of tests, modifying, in real time, the execution sequence including: executing a delay instead of the group of tests, wherein the delay is related to the group of tests.
  • Obscurely Rendering Content Using Masking Techniques

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  • US Patent:
    20150371014, Dec 24, 2015
  • Filed:
    Jun 25, 2015
  • Appl. No.:
    14/750432
  • Inventors:
    - Plano TX, US
    Satyadev Rajesh Patel - Palo Alto CA, US
    Scott Richardson - Portland OR, US
    Shaul Teplinsky - San Francisco CA, US
  • International Classification:
    G06F 21/10
    G09G 5/377
    G06T 5/00
  • Abstract:
    Exemplary embodiments relate to methods, apparatus, and computer-readable media storing instructions for displaying content. An exemplary method comprises receiving source content, constructing a mask that segments the source content into at least a first segment and a second segment, identifying a masking technique, generating a first transformed image by applying the masking technique to the first segment, the first transformed image being different from the source content, generating a second transformed image by applying the masking technique to the second segment, the second transformed image being different from the source content and the first transformed image, and displaying the first transformed image and the second transformed image as frames in a repeating series of frames to thereby approximate the source content.
  • Obscurely Rendering Content Using Masking Techniques

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  • US Patent:
    20150371611, Dec 24, 2015
  • Filed:
    Jun 19, 2015
  • Appl. No.:
    14/744997
  • Inventors:
    - Plano TX, US
    Satyadev Rajesh Patel - Palo Alto CA, US
    Scott Richardson - Plano TX, US
    Shaul Teplinsky - San Francisco CA, US
  • International Classification:
    G09G 5/377
  • Abstract:
    Exemplary embodiments relate to methods, apparatus, and computer-readable media storing instructions for displaying content. An exemplary method comprises receiving source content, identifying a mask that segments the source content into at least a first segment and a second segment, the identifying including specifying one or more parameters associated with the mask, identifying one or more masking techniques, associating the source content with obscuration information and one or more usage rules, the obscuration information including information corresponding to the mask, information corresponding to the one or more parameters, and information corresponding to the one or more masking techniques, and transmitting the source content, the one or more usage rules, and the obscuration information to at least one recipient computing device.
  • Obscurely Rendering Content Using Image Splitting Techniques

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  • US Patent:
    20150371613, Dec 24, 2015
  • Filed:
    Jun 25, 2015
  • Appl. No.:
    14/751102
  • Inventors:
    - Plano TX, US
    Michael Charles Raley - Plano TX, US
    Steven L. Horowitz - Oakland CA, US
    Shaul Teplinsky - San Francisco CA, US
  • International Classification:
    G09G 5/395
    G06T 1/60
    G06F 21/10
    G09G 5/02
  • Abstract:
    Exemplary embodiments relate to methods, apparatus, and computer-readable media storing instructions for providing frames for rendering on a display, the frames including a first frame comprising first pixel data, a second frame comprising second pixel data, and a third frame comprising third pixel data, the first pixel data comprising input values for color components including a first input value, the second pixel data comprising a second input value, and the third pixel data comprising a third input value. An exemplary method comprises determining the second input value such that a second output luminance corresponds to the minimum of double a first output luminance and a maximum output luminance, determining the third input value such that a third output luminance corresponds to double the first output luminance minus the second output luminance, and providing the second frame and the third frame for rendering on a display.

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