Sheldon D Haynie

US Patent:

8445353, May 21, 2013

Filed:

Sep 29, 2009

Appl. No.:

12/586836

Inventors:

Venkat Raghavan - Union City CA, US
Sheldon Haynie - San Martin CA, US
Andrew Strachan - Santa Clara CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/20

US Classification:

438381, 257E27025

Abstract:

A method for integrating a metal-insulator-metal (MIM) capacitor and a thin film resistor in an integrated circuit is provided that includes depositing a first metal layer outwardly of a semiconductor wafer substrate. A portion of the first metal layer forms a bottom plate for a MIM capacitor. A second metal layer is deposited outwardly of the first metal layer. A first portion of the second metal layer forms a top plate for the MIM capacitor and a second portion of the second metal layer forms contact pads for a thin film resistor.

US Patent:

8492255, Jul 23, 2013

Filed:

Jan 6, 2011

Appl. No.:

12/986107

Inventors:

Sheldon D. Haynie - San Martin CA, US
Ann Gabrys - Santa Clara CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/28

US Classification:

438576, 438534, 438571, 257E21238, 257E21351

Abstract:

A Schottky diode with a small footprint and a high-current carrying ability is fabricated by forming an opening that extends into an n-type semiconductor material. The opening is then lined with a metallic material such as platinum. The metallic material is then heated to form a salicide region where the metallic material touches the n-type semiconductor material.

US Patent:

20220367388, Nov 17, 2022

Filed:

May 12, 2021

Appl. No.:

17/318556

Inventors:

- Dallas TX, US
Sheldon Douglas Haynie - Myrtle Beach SC, US
Ujwal Radhakrishna - Sunnyvale CA, US

International Classification:

H01L 23/64
H01L 29/40
H01L 29/78
H01L 29/66

Abstract:

A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

US Patent:

20210074839, Mar 11, 2021

Filed:

Sep 6, 2019

Appl. No.:

16/563366

Inventors:

- Dallas TX, US
Sheldon Douglas Haynie - Morgan Hill CA, US

International Classification:

H01L 29/78
H01L 29/06
H01L 29/10
H01L 29/40
H01L 21/74
H01L 21/762
H01L 21/765
H01L 29/66

Abstract:

Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.

US Patent:

20200274002, Aug 27, 2020

Filed:

Feb 21, 2019

Appl. No.:

16/281626

Inventors:

- Dallas TX, US
Sheldon Douglas Haynie - Morgan Hill CA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/808
H01L 29/423
H01L 29/40
H01L 29/78
H01L 29/66

Abstract:

An IC with a split-gate transistor includes a substrate doped the second conductivity type having a semiconductor surface layer doped the first conductivity type. The transistor includes a first doped region formed as an annulus, a second doped region including under the first doped region, and a third doped region under the second doped region, all coupled together and doped the second conductivity type. A fourth doped region doped the first conductivity type is above the third doped region. A fifth doped region doped the first conductivity type is outside the annulus. Sixth doped regions doped the first conductivity type include a first sixth doped region surrounded by the annulus in the semiconductor surface layer and a second sixth doped region in the fifth doped region. Field oxide includes a field oxide portion between the fifth and the first doped region. A field plate is on the field oxide portion.