Shelley Chen

US Patent:

7752411, Jul 6, 2010

Filed:

Jul 21, 2006

Appl. No.:

11/491312

Inventors:

Randy B. Osborne - Beaverton OR, US
Shelley Chen - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711168, 710 35, 710 39, 370235

Abstract:

In some embodiments, a chip includes a link interface, monitoring circuitry to provide an activity indicator that is indicative of activity of the chip, and scheduling circuitry to schedule commands. The chip also includes mode selection circuitry to select a first mode or a second mode for the scheduling circuitry depending on the activity indicator, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules at least one consolidated command to represent more than one of the separate single commands. Other embodiments are described.

US Patent:

20070150687, Jun 28, 2007

Filed:

Dec 23, 2005

Appl. No.:

11/318028

Inventors:

Shelley Chen - Hillsboro OR, US
Randy Osborne - Beaverton OR, US

International Classification:

G06F 13/00

US Classification:

711168000

Abstract:

In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in response thereto to select a first or a second mode for the scheduling circuitry, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules consolidated commands to represent more than one separate single command. Other embodiments are described.